參數(shù)資料
型號： MB91F467SAPMC-GSE2
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP176
封裝： 24 X 24 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, PLASTIC, LQFP-176
文件頁數(shù)： 72/144頁
文件大?。?/td> 5502K
代理商： MB91F467SAPMC-GSE2
MB91460S Series
DS07-16617-3E
33
3.2.
Flash access timing settings in CPU mode
The following tables list all settings for a given maximum Core Frequency (through the setting of CLKB or
maximum clock modulation) for Flash read and write access.
3.2.1.
Flash read timing settings (synchronous read)
3.2.2.
Flash write timing settings (synchronous write)
3.3.
Address mapping from CPU to parallel programming mode
The following tables show the calculation from CPU addresses to flash macro addresses which are used in
parallel programming.
3.3.1.
Address mapping MB91F467SA
Note: FA result is without 20:0000h offset for parallel Flash programming .
Set offset by keeping FA[21] = 1 as described in section “Parallel Flash programming mode
”.
Core clock (CLKB)
ATD
ALEH
EQ
WEXH
WTC
Remark
to 24 MHz
0
1
to 48 MHz
0
1
0
2
to 96 MHz
1
3
0
4
to 100 MHz
1
3
0
4
Core clock (CLKB)
ATD
ALEH
EQ
WEXH
WTC
Remark
to 32 MHz
1
0
1
0
4
to 48 MHz
1
0
3
0
5
to 64 MHz
1
3
0
6
to 96 MHz
1
3
0
7
to 100 MHz
1
3
0
7
CPU Address
(addr)
Condition
Flash
sectors
FA (flash address) Calculation
14:0000h
to
14:FFFFh
addr[2]==0
SA0, SA2, SA4, SA6
(8 Kbyte)
FA := addr - addr%00:4000h + (addr%00:4000h)/2
- (addr/2)%4 + addr%4 - 05:0000h
14:0000h
to
14:FFFFh
addr[2]==1
SA1, SA3, SA5, SA7
(8 Kbyte)
FA := addr - addr%00:4000h + (addr%00:4000h)/2
- (addr/2)%4 + addr%4 - 05:0000h
+ 00:2000h
04:0000h
to
13:FFFFh
addr[2]==0
SA8, SA10, SA12, SA14,
SA16, SA18, SA20, SA22
(64 Kbyte)
FA := addr - addr%02:0000 + (addr%02:0000h)/2
- (addr/2)%4 + addr%4 + 0C:0000h
04:0000h
to
13:FFFFh
addr[2]==1
SA9, SA11, SA13, SA15,
SA17, SA19, SA21, SA23
(64 Kbyte)
FA := addr - addr%02:0000h + (addr%02:0000h)/2
- (addr/2)%4 + addr%4 + 0C:0000h
+ 01:0000h
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