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參數(shù)資料
| 型號： | MB91F313APMC-GE1 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 33 MHz, RISC MICROCONTROLLER, PQFP120 |
| 封裝： | 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, LFQFP-120 |
| 文件頁數(shù)： | 60/72頁 |
| 文件大?。?/td> | 1975K |
| 代理商： | MB91F313APMC-GE1 |
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MB91313/A Series
DS07-16706-3E
63
When operating in slave mode
(VDDE
= 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = 40 °C to + 85 °C)
*1 : For use at over 100 kHz, set the resource clock to 6 MHz or higher.
*2 : R and C represent the pull-up resistance and load capacitance of the SCL and SDA output lines, respectively.
*3 : M = Resource clock cycle (ns)
*4 : A high-speed mode I2C bus device can be used on a standard mode I2C bus system as long as the device
satisfies the requirement of “tSUDAT
≥ 250 ns”.
When a device does not extend the “L” period of the SCL signal, the next data must be output to the SDA line
within 1250 ns (maximum SDA/SCL rise time
+ tSUDAT) from when the SCL line is released.
I2C timing
Parameter
Symbol Conditions
Typical mode
High-speed
mode*1
Unit
Remarks
Min
Max
Min
Max
SCL clock frequency
fSCL
R
= 1 k,
C
= 50 pF*2
0
100
0
400
kHz
“L” period of SCL clock
tLOW
4.7
1.3
s
“H” period of SCL clock
tHIGH
4.0
0.6
s
Bus free time between
“STOP condition” and
“START condition”
tBUS
4.7
1.3
s
SCL
↓ → SDA output delay
time
tDLDAT
5
× M*3
5
× M*3 ns
“Repeated START condition”
setup time SCL
↑ → SDA ↓
tSUSTA
4.7
0.6
s
“Repeated START condition”
hold time SDA
↓ → SCL ↓
tHDSTA
4.0
0.6
s
The first clock
pulse is generat-
ed after this.
“STOP condition” setup time
SCL
↑ → SDA ↑
tSUSTO
4.0
0.6
s
SDA data input hold time
(vs. SCL
↓)
tHDDAT
2
× M*3
2
× M*3
s
SDA data input setup time
(vs. SCL
↑)
tSUDAT
250
100*4
ns
tHDSTA
tSUSTO
tHDSTA
tSUSTA
tSUDAT
tHDDAT
0.8 VDDE
SCL
SDA
tHIGH
tLOW
tBUS
0.2 VDDE
fSCL
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相關代理商/技術參數(shù) |
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|---|---|
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