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參數(shù)資料
| 型號： | MB91F313APMC-GE1 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 33 MHz, RISC MICROCONTROLLER, PQFP120 |
| 封裝： | 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, LFQFP-120 |
| 文件頁數(shù)： | 58/72頁 |
| 文件大?。?/td> | 1975K |
| 代理商： | MB91F313APMC-GE1 |
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MB91313/A Series
DS07-16706-3E
61
(11) I2C timing
When operating in master mode
(VDDE
= 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = 40 °C to + 85 °C)
*1 : R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp
indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2 : The maximum tHDDAT must satisfy that it doesn't extend at least “L” period (tLOW) of device's SCL signal.
*3 : A high-speed mode I2C bus device can be used on a standard mode I2C bus system as long as the device
satisfies the requirement of “tSUDAT
≥ 250 ns”.
*4 : tCYCP is the peripheral clock cycle time. To use I2C, set the peripheral bus clock at 8 MHz or more.
Parameter
Symbol
Pin name
Conditions
Typical mode
High-speed
mode*1
Unit
Min
Max
Min
Max
SCL clock frequency
fSCL
SCKn
(SCLn)
CL
= 50 pF,
R
= (Vp/IOL)*1
01000400
kHz
“(Repeated) START condition”
hold time SDA
↓ → SCL ↓
tHDSTA
SOTn
(SDAn)
SCKn
(SCLn)
4.0
0.6
s
SCL clock “L” width
tLOW
SCKn
(SCLn)
4.7
1.3
s
SCL clock “H” width
tHIGH
SCKn
(SCLn)
4.0
0.6
s
“Repeated START
condition” setup time
SCL
↑→ SDA ↓
tSUSTA
SCKn
(SCLn)
4.7
0.6
s
Data hold time
SCL
↓ → SDA ↓ ↑
tHDDAT
SOTn
(SDAn)
SCKn
(SCLn)
03.45*2
00.9*3
s
Data setup time
SDA
↓ ↑ → SCL ↑
tSUDAT
SOTn
(SDAn)
SCKn
(SCLn)
250
100
ns
“STOP condition” setup time
SCL
↑ → SDA ↑
tSUSTO
SOTn
(SDAn)
SCKn
(SCLn)
4.0
0.6
s
Bus free time between
“STOP condition” and
“START condition”
tBUF
4.7
1.3
s
Noise filter
tSP
2 tCYCP*4
2 tCYCP*4
ns
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|---|---|
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