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參數(shù)資料
| 型號： | MB90W224AZF |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, UVPROM, 16 MHz, MICROCONTROLLER, CQFP120 |
| 封裝： | CERAMIC, QFP-120 |
| 文件頁數(shù)： | 46/105頁 |
| 文件大?。?/td> | 1700K |
| 代理商： | MB90W224AZF |
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45
MB90220 Series
6. PWC (Pulse Width Count) Timer
The PWC (pulse width count) timer is a 16-bit multifunction up-count timer with an input-signal pulse-width count
function and a reload timer function. The hardware configuration of this module is a 16-bit up-count timer, an
input pulse divider with divide ratio control register, four count input pins, and a 16-bit control register. Using
these components, the PWC timer provides the following features:
Timer functions:
An interrupt request can be generated at set time intervals.
Pulse signals synchronized with the timer cycle can be output.
The reference internal clock can be selected from among three internal clocks.
Pulse-width count functions:
The time between arbitrary pulse input events can be counted.
The reference internal clock can be selected from among three internal clocks.
Various count modes:
“H” pulse width (
↑ to ↓)/“L” pulse width (↓ to ↑)
Rising-edge cycle (
↑ to ↑/Falling-edge cycle (↓ to ↓)
Count between edges (
↑ or ↓ to ↓ or ↑)
Cycle count can be performed by 22n division (n = 1, 2, 3, 4) of the input
pulse, with an 8 bit input divider.
An interrupt request can be generated once counting has been performed.
The number of times counting is to be performed (once or subsequently) can
be selected.
The MB90220 series has four channels for this module.
(1) Register Configuration
bit15
bit14
bit13
bit12
bit11
bit10
bit9
STRT
STOP
EDIR
EDIE
OVIR
OVIE
ERR
POUT
bit8
000051 H
000053 H
000055 H
000057 H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
CKS1
CKS0
PIS1
PIS0
S/C
MOD1
MOD0
bit0
000050 H
000052 H
000054 H
000056 H
001F01 H
001F03 H
001F05 H
001F07 H
001F00 H
001F02 H
001F04 H
001F06 H
PWCSR0
PWCSR1
PWCSR2
PWCSR3
00000000B
PWCSR0
PWCSR1
PWCSR2
PWCSR3
00000000B
PWCR0
PWCR1
PWCR2
PWCR3
00000000B
PWCR0
PWCR1
PWCR2
PWCR3
00000000B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Register name Address
(R/W)
(R)
(R/W)
(R)
(R/W)
Initial value
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
(R/W)
PWC Control Status Register 0 to 3 (PWCSR0 to PWCSR3)
PWC Data Buffer Register 0 to 3 (PWCR0 to PWCR3)
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