
25
MB90220 Series
s I/O MAP
(Continued)
Address
Register
name
Access
Resouce
name
Initial value
000000H*3
Port 0 data register
PDR0
R/W
Port 0
XXXXXXX X
000001H*3
Port 1 data register
PDR1
R/W
Port 1
XXXXXXX X
000002H*3
Port 2 data register
PDR2
R/W
Port 2
XXXXXXX X
000003H*3
Port 3 data register
PDR3
R/W
Port 3
XXXXXXX X
000004H*3
Port 4 data register
PDR4
R/W
Port 4
XXXXXXX X
000005H*3
Port 5 data register
PDR5
R/W
Port 5
XXXXXXX X
000006H
Port 6 data register
PDR6
R/W
Port 6
1111111 1
000007H
Port 7 data register
PDR7
R
Port 7
XXXXXXX X
000008H
Port 8 data register
PDR8
R/W
Port 8
XXXXXXX X
000009H
Port 9 data register
PDR9
R/W
Port 9
1111111 1
00000AH
Port A data register
PDRA
R/W
Port A
XXXXXXX X
00000BH
Port B data register
PDRB
R/W
Port B
XXXXXXX X
00000CH
Port C data register
PDRC
R/W
Port C
– – XXXXX X
00000DH
to 0FH
(Reserved area)*1
000010H*3
Port 0 data direction register
DDR0
R/W
Port 0
0000000 0
000011H*3
Port 1 data direction register
DDR1
R/W
Port 1
0000000 0
000012H*3
Port 2 data direction register
DDR2
R/W
Port 2
0000000 0
000013H*3
Port 3 data direction register
DDR3
R/W
Port 3
0000000 0
000014H*3
Port 4 data direction register
DDR4
R/W
Port 4
0000000 0
000015H*3
Port 5 data direction register
DDR5
R/W
Port 5
0000000 0
000016H
Port 6 analog input enable register
ADER0
R/W
Port 6
1111111 1
000017H
Port 7 data direction register
DDR7
R/W
Port 7
1111111 1
000018H
Port 8 data direction register
DDR8
R/W
Port 8
0000000 0
000019H
Port 9 analog input enable register
ADER1
R/W
Port 9
1111111 1
00001AH
Port A data direction register
DDRA
R/W
Port A
0000000 0
00001BH
Port B data direction register
DDRB
R/W
Port B
0000000 0
00001CH
Port C data direction register
DDRC
R/W
Port C
–– 00000 0
00001DH
to 1FH
(Reserved area)*1
000020H
Mode control register 0
UMC0
R/W
UART 0 (ch.0)
0000010 0
000021H
Status register 0
USR0
R/W
0001000 0
000022H
Input data register 0
/output data register 0
UIDR0
/UODR0
R/W
XXXXXXX X