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參數(shù)資料
| 型號(hào)： | MB90W224AZF |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, UVPROM, 16 MHz, MICROCONTROLLER, CQFP120 |
| 封裝： | CERAMIC, QFP-120 |
| 文件頁數(shù)： | 34/105頁 |
| 文件大?。?/td> | 1700K |
| 代理商： | MB90W224AZF |
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MB90220 Series
34
(Continued)
: EI2OS is supported (with stop request).
: EI2OS is supported (without stop request).
: EI2OS is supported; however, since two interrupt sources are allocated to a single ICR, in case EI2OS is used
for one of the two, EI2OS and ordinary interrupt are not both available for the other (with stop request).
: EI2OS is supported; however, since two interrupt sources are allocated to a single ICR, in case EI2OS is used
for one of the two, EI2OS and ordinary interrupt are not both available for the other (without stop request).
: EI2OS is not supported.
Note: Since the interrupt sources having interrupt vector Nos. 15 to 18, 20, and 25 to 28 are OR’ed, respectively,
select them by means of the interrupt enable bits of each resource.
If EI2OS is used with the above-mentioned interrupt sources OR’ed with the interrupt vector Nos. 15 to 18,
20, and 25 to 28, be sure to activate one of the interrupt sources.
Also in this case, a request flag in the same series as the one interrupt source is likely to be cleared
automatically by EI2OS.
Assume for example that an interrupt for compare 4 of the interrupt vector No. 25 is activated at this time by
ICR07, so that the compare 6 is disabled. If EI2OS is activated at this time by ICR07, so that the compare 6
interrupt takes place during generation of or simultaneously with the compare 4 interrupt, not only the interrupt
flag for the compare 4 but also that for the compare 6 will be automatically cleared after EI2OS is automatically
transferred due to the compare 4 interrupt.
Interrupt source
EI2OS
support
Interrupt vector
Interrupt control
register
No.
Address
ICR
Address
UART0 (ch.0) reception completed
#39
27H
FFFF60H
ICR14
0000BEH
Delay interrupt generation module
×
#42
2AH
FFFF54H
ICR15
0000BFH
Stack fault
×
#255
FFH
FFFC00H
——
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