
MB90820 Series
44
5.
16-bit reload timer (x 2)
The 16-bit reload timer provides two operating mode, internal clock mode and event count mode. In each
operating mode, the 16-bit down counter can be reloaded (reload mode) or stopped by underflow (one-shot
mode).
Output pins TO1 and TO0 are able to output different waveform according to the counter operating mode. TO1
and TO0 toggles when counter underflows if counter is operated as reload mode. TO1 and TO0 output specified
level (H or L) during counting if the counter is in one-shot mode.
Features of the 16-bit reload timer :
Interrupt when timer underflows
Supports for EI2OS
Internal clock operating mode :
Three internal count clocks can be selected.
Counter can be activated by software or external trigger (signal at TIN1 and TIN0 pins).
Counter can be reloaded or stopped when underflow after activated.
Event count operating mode :
Counter counts down one by one with specified edge at TIN1 and TIN0 pins.
Counter can be reloaded or stopped when underflow.
(1) Register configuration
Note : Registers TMR0, TMR1/TMRD0, TMRD1 are word access only.
15
14
13
12
11
10
9
8
Bit
16-bit Timer Register/16-bit Reload Timer Register (Upper)
7
6
5
4
3
2
1
0
Bit
16-bit Timer Register/16-bit Reload Timer Register (Lower)
Address: ch0 000085H
ch1 000089H
TMR0
, TMR1 /
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Initial value
Read/write
Address: ch0 000084H
ch1 000088H
Initial value
Read/write
TMR0
, TMR1 /
D15
D14
D13
D12
D11
D10
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
TMRD0
, TMRD1
TMRD0
, TMRD1
15
14
13
12
11
10
9
8
Bit
Timer Control Status Register (Upper)
7
6
5
4
3
2
1
0
Bit
Timer Control Status Register (Lower)
Address: ch0 000083H
ch1 000087H
TMCSRH0
,
R/W
0
R/W
0
R/W
0
R/W
0
Initial value
Read/write
Address: ch0 000082H
ch1 000086H
Initial value
Read/write
TMCSRL0
,
CSL1
CSL0
MOD2 MOD1
MOD0 OUTE
OUTL RELD
INTE
UF
CNTE
TRG
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
FSEL
R/W
1
XX
X
TMCSRH1
TMCSRL1