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參數(shù)資料
| 型號(hào)： | MB90613APF |
| 廠商： | FUJITSU LTD |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 60/91頁(yè) |
| 文件大?。?/td> | 1537K |
| 代理商： | MB90613APF |
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63
MB90610A Series
(10) I/O Expansion Serial Timing
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Notes: These are the AC characteristics for CLK synchronous mode.
CL is the load capacitance connected to the pin at testing.
tCP is the machine cycle period (unit: ns).
Parameter
Sym-
bol
Pin name
Conditions
Value
Unit
Remarks
Min.
Max.
Serial clock cycle time
tSCYC
SCK0 to 2
—
8 tCP
—ns
CL = 80 pF + 1
TTL for the
internal shift
clock mode
output pin.
SCK
↓ → SOT delay
time
tSLOV
SCK0 to 2
SOT0 to 2
VCC = +5.0 V±10%
–80
80
ns
VCC = +3.0 V±10%
–120
120
ns
Valid SIN
→ SCK ↑
tIVSH
SCK0 to 2
SIN0 to 2
VCC = +5.0 V±10%
100
—
ns
VCC = +3.0 V±10%
200
—
ns
SCK
↑ → valid SIN hold
time
tSHIX
SCK0 to 2
SIN0 to 2
VCC = +5.0 V±10%
60
—
ns
VCC = +3.0 V±10%
120
—
ns
Serial clock “H” pulse
width
tSHSL
SCK0 to 2
—
4 tCP
—ns
CL = 80 pF + 1
TTL for the
external shift
clock mode
output pin.
Serial clock “L” pulse
width
tSLSH
SCK0 to 2
—
4 tCP
—ns
SCK
↓ → SOT delay
time
tSLOV
SCK0 to 2
SOT0 to 2
VCC = +5.0 V±10%
—
150
ns
VCC = +3.0 V±10%
—
200
ns
Valid SIN
→ SCK ↑
tIVSH
SCK0 to 2
SIN0 to 2
VCC = +5.0 V±10%
60
—
ns
VCC = +3.0 V±10%
120
—
ns
SCK
↑ → valid SIN hold
time
tSHIX
SCK0 to 2
SIN0 to 2
VCC = +5.0 V±10%
60
—
ns
VCC = +3.0 V±10%
120
—
ns
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MB90622A | 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontroller |
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| MB90632A | 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontroller |
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