參數(shù)資料
型號(hào)： MB90613APF
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁數(shù)： 35/91頁
文件大?。?/td> 1537K
代理商： MB90613APF
40
MB90610A Series
9.
Watchdog Timer and Timebase Timer Functions
The watchdog timer consists of a 2-bit watchdog counter, a control register, and a watchdog reset controller.
The watchdog counter uses the carry-up signal from the 18-bit timebase timer as its clock source. In addition
to the 18-bit timer, the timebase timer contains an interval interrupt control circuit. The timebase timer uses the
main clock, regardless of the value of the MCS bit in the CKSCR register.
(1) Register Configuration
(2) Block Diagram
bit
Read/write
Initial value
PONR STBR WRST ERST SRST WTE
WT1
WT0
WDTC
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(W)
(1)
(W)
(1)
(W)
(1)
76543210
Watchdog timer control register
Address : 0000A8H
bit
Read/write
Initial value
Reserved
—
TBIE TBOF TBR TBC1 TBC0
TBTC
(—)
(1)
(—)
(R/W)
(0)
(R/W)
(0)
(W)
(1)
(R/W)
(0)
(R/W)
(0)
15
14
13
12
11
10
9
8
Timebase timer control register
Address : 0000A9H
TBTC
TBC1
TBC0
TBR
TBIE
TBOF
PONR
STBR
WRST
ERST
SRST
Selector
AND
Q
Selector
2-bit counter
CLR
Watchdog reset
activation circuit
WT1
WDTC
WT0
WTE
212
Timebase
interrupt
S
R
214
216
219
TBTRES
Timebase timer
Clock input
214 216 219
OF
Main clock
(OSC oscillator)
WDGRST
To internal reset
activation circuit
From power-on detection
From hardware standby
control circuit
RST pin
From the RST bit of the
STBYC register
F
2 MC-16
bus
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