參數(shù)資料
型號(hào)： MB90613APF
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁數(shù)： 32/91頁
文件大?。?/td> 1537K
代理商： MB90613APF
38
MB90610A Series
7.
DTP/External Interrupts
The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the F2MC-16L
CPU. The DTP receives DMA and interrupt processing requests from external peripherals and passes the
requests to the F2MC-16L CPU to activate the extended intelligent I/O service or interrupt processing. Two
request levels (“H” and “L”) are provided for extended intelligent I/O service. For external interrupt requests,
generation of interrupts on a rising or falling edge as well as on “H”, “L” levels can be selected, giving a total of
four types.
(1) Register Configuration
(2) Block Diagram
bit
Read/write
Initial value
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
ENIR
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
76543210
Interrupt/DTP enable register
Address : 000028H
bit
Read/write
Initial value
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
EIRR
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
15
14
13
12
11
10
9
8
Interrupt/DTP register
Address : 000029H
bit
Read/write
Initial value
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
15
14
13
12
11
10
9
8
Request level setting register (upper)
Address : 00002BH
bit
Read/write
Initial value
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
ELVR
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
76543210
Request level setting register (lower)
Address : 00002AH
8
Interrupt/DTP enable register
Interrupt/DTP register
Request level setting register
Gate
Request F/F
Edge detect circuit
Request input
Interrupt input
F2MC-16 bus
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