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參數(shù)資料
| 型號(hào)： | MB86064 |
| 廠商： | FUJITSU LTD |
| 元件分類： | DAC |
| 英文描述： | Dual 14-bit 1GSa/s DAC |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 14-BIT DAC, PBGA120 |
| 封裝： | 12 X 12 MM, PLASTIC, EFBGA-120 |
| 文件頁(yè)數(shù)： | 2/4頁(yè) |
| 文件大?。?/td> | 123K |
| 代理商： | MB86064 |
October 2004 Version 1.1
FME/MS/DAC80/FL/5085
MB86064
Dual 14-bit 1GSa/s DAC
Page 2 of 4
Production
Copyright 2004 Fujitsu Microelectronics Europe GmbH
Disclaimer:
The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before
ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.
Functional Overview
The MB86064 is a high performance Dual 14-bit 1GSa/s DAC. In addition to two DAC cores the
device features a host of features designed to help both system integration and operation. A
functional block diagram is shown in Figure 1. Analog performance at high frequencies is enhanced
by novel current switch and switch driver designs which provide constant data-independent switching
delay, reducing jitter and distortion.
Figure 1 MB86064 Functional Block Diagram
The device requires an input clock at half the DAC conversion rate as each DAC core is clocked on
both edges of the input clock. Each DAC core can be regarded as two interleaved DACs, each
running at half rate. The main reason for adopting this approach is that the switch driver inherently
includes a multiplex function through its two input ports. Compared to a conventional switch driver
this allows twice as long to acquire and convert, though because the two paths share current sources
they match exactly at low frequencies. A characteristic of this architecture is a suppressed image
appearing reflected about Fs(dac)/4 of Fclk-Fsig. Duty cycle error in the input clock will exacerbate
this image, but can be minimised by trimming the differential DC offset at the clock input pins.
The big advantage of this approach compared to a single DAC running at half the rate is much
reduced sinx/x roll off, which gives increased output power and better in-band flatness when
generating high output frequencies (e.g. 200MHz and above). This is illustrated in Figure 2 as line 1.
An alternative approach using a return-to-zero output stage has the same sinx/x roll off (and switch
driver speed) but 6dB lower output power and a large image at Fclk-Fout. See Line 2.
Port A data input
14-bit LVDS
Port B data input
14-bit LVDS
Waveform
Memory
A
(16K Points)
W
Waveform
Memory
B
(16K Points)
RF Clock input
e.g. 500MHz
Loop clock input
LVDS
Loop clock output
LVDS
Clock output 2
LVDS
Clock output 1
LVDS
4-wire Serial Control Interface
Control Interface
1.8V LVCMOS
Analog output A
Analog output B
EFBGA-120
÷
1, 2, 4, 8
DAC A
(14-bit)
DAC B
(14-bit)
÷
1, 2, 4, 8
Double-Edge
clocked
(1GSa/s)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB86064_09 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:High-Performance Digital to Analog Converters |
| MB86064PB-G | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual 14-bit 1GSa/s DAC Development Kit |
| MB86064PB-GE1 | 功能描述:DAC 14BIT 1GSA/S DUAL 12-EFBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:2,400 系列:- 設(shè)置時(shí)間:- 位數(shù):18 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:3 電壓電源:模擬和數(shù)字 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:36-TFBGA 供應(yīng)商設(shè)備封裝:36-TFBGA 包裝:帶卷 (TR) 輸出數(shù)目和類型:* 采樣率（每秒）:* |
| MB86064PB-G-K1E1 | 制造商:FUJITSU 功能描述: 制造商:FUJITSU 功能描述:DAC 14BIT 1GSA/S DUAL |
| MB86065 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:High-Performance Digital to Analog Converters |
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