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參數(shù)資料
| 型號(hào)： | MB81ES653225 |
| 廠商： | Fujitsu Limited |
| 英文描述： | Consumer/Embedded Application Specific Memory for SiP |
| 中文描述： | 消費(fèi)/嵌入式SIP應(yīng)用程序特定的內(nèi)存 |
| 文件頁(yè)數(shù)： | 30/44頁(yè) |
| 文件大?。?/td> | 485K |
| 代理商： | MB81ES653225 |
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MB81ES653225-12/-12L
30
2.
BASE VALUES FOR CLOCK COUNT/LATENCY
* : Actual clock count of t
RC
(l
RC
) will be sum of clock count of t
RAS
(l
RAS
) and t
RP
(l
RP
) .
3.
CLOCK COUNT FORMULA
Note : All base values are measured from the clock edge at the command input to the clock edge for the next
command input. All clock counts are calculated by a simple formula : clock count equals base value divided
by clock period (round off to a whole number) .
4.
LATENCY (The latency values on these parameters are fixed regardless of clock period.)
Parameter
Symbol MB81ES653225-12
Parameter
Symbol
Value
Unit
Min
Max
110000
RAS Cycle Time
*
t
RC
80
ns
RAS Precharge Time
t
RP
20
ns
RAS Active Time
t
RAS
60
ns
RAS to CAS Delay Time
t
RCD
20
ns
Write Recovery Time
t
WR
11.7
ns
RAS to RAS Bank Active Delay Time
t
RRD
20
ns
Data-in to Precharge Lead Time
t
DPL
18.5/20
1 cyc
+
t
RP
2 cyc
+
t
RP
2 cyc
+
t
RP
2 cyc
+
t
RP
20
ns
Data-in to Active/Refresh Command
Period
CL
=
2
-12
t
DAL2
ns
-12L
CL
=
3
-12
t
DAL3
ns
-12L
Mode Register Set Cycle Time
t
RSC
ns
MB81ES653225-12L
Unit
CKE to Clock Disable
l
CKE
1
1
cycle
DQM to Output in High-Z
l
DQZ
2
2
cycle
DQM to Input Data Delay
l
DQD
0
0
cycle
Last Output to Write Command Delay
l
OWD
2
2
cycle
Write Command to Input Data Delay
l
DWD
0
0
cycle
Precharge to Output in High-Z Delay
CL
=
2
CL
=
3
CL
=
2
CL
=
3
l
ROH2
2
2
cycle
l
ROH3
3
3
cycle
Burst Stop Command to Output
in High-Z Delay
l
BSH2
2
2
cycle
l
BSH3
3
3
cycle
CAS to CAS Delay (Min)
l
CCD
1
1
cycle
CAS Bank Delay (Min)
l
CBD
1
1
cycle
Clock
≥
(Round up a whole number)
Base Value
Clock Period
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