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參數(shù)資料
| 型號： | MAX9384EWP |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | ECL/PECL Dual Differential 2:1 Multiplexer |
| 中文描述： | DUAL 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO20 |
| 封裝： | 0.300 INCH, SOIC-20 |
| 文件頁數(shù)： | 9/10頁 |
| 文件大?。?/td> | 235K |
| 代理商： | MAX9384EWP |
Applications Information
Output Termination
Terminate the outputs through 50
to V
CC
- 2V or use
equivalent Thevenin terminations. Terminate each Q_
and
Q_
output with identical termination on each for
minimal distortion. When a single-ended signal is taken
from the differential output, terminate both Q_ and
Q_
.
Ensure that output currents do not exceed the current
limits as specified in the
Absolute Maximum Ratings
table. Under all operating conditions, the device
’
s total
thermal limits should be observed.
Supply Bypassing
Bypass each V
CC
to V
EE
with high-frequency surface-
mount ceramic 0.1μF and 0.01μF capacitors. Place the
capacitors as close to the device as possible, with the
0.01μF capacitor closest to the device pins.
Use multiple vias when connecting the bypass capaci-
tors to ground. When using the V
BB0
or V
BB1
reference
outputs, bypass each one with a 0.01μF ceramic
capacitor to V
CC
. If the V
BB0
or V
BB1
reference outputs
are not used, they can be left open.
Traces
Circuit board trace layout is very important to maintain
the signal integrity of high-speed differential signals.
Maintaining integrity is accomplished in part by reduc-
ing signal reflections and skew, and increasing com-
mon-mode noise immunity.
Signal reflections are caused by discontinuities in the
50
characteristic impedance of the traces. Avoid dis-
continuities by maintaining the distance between differ-
ential traces, not using sharp corners or using vias.
Maintaining distance between the traces also increases
common-mode noise immunity. Reducing signal skew
is accomplished by matching the electrical length of
the differential traces.
Chip Information
TRANSISTOR COUNT: 485
PROCESS: Bipolar
M
ECL/PECL Dual Differential 2:1 Multiplexer
_______________________________________________________________________________________
9
Functional Diagram
Q0
Q0
MUX 0
D0a
D0a
D0b
D0b
120k
120k
V
CC
V
EE
Q1
Q1
MUX 1
D1a
D1a
D1b
D1b
120k
120k
V
CC
V
EE
SEL0
COM_SEL
SEL1
V
EE
210k
MAX9384
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9384EWP/GG8 | 制造商:Maxim Integrated Products 功能描述: |
| MAX9384EWP/GH9 | 制造商:Maxim Integrated Products 功能描述:ECL/PECL DUAL DIFFERENTIAL 2:1 MULTIPLEXER - Rail/Tube |
| MAX9384EWP/GH9-T | 制造商:Maxim Integrated Products 功能描述:ECL/PECL DUAL DIFFERENTIAL 2:1 MULTIPLEXER - Tape and Reel |
| MAX9384EWP+ | 制造商:Maxim Integrated Products 功能描述:CLOCK MLTPLXR 4-IN LVECL/LVPECL 20SOIC - Rail/Tube |
| MAX9384EWP+T | 制造商:Maxim Integrated Products 功能描述:CLOCK MLTPLXR 4-IN LVECL/LVPECL 20SOIC - Tape and Reel |
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