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參數(shù)資料
| 型號： | MAX9273GTL/V+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 31/49頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SERIALIZER 22BIT GMSL 40TQFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | * |
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MAX9273
22-Bit GMSL Serializer with Coax or
STP Cable Drive
37
Maxim Integrated
Configuration Link
The control channel can operate in a low-speed mode
called configuration link in the absence of a clock input.
This allows a microprocessor to program configura-
tion registers before starting the video link. An internal
oscillator provides the clock for configuration link. Set
CLINKEN = 1 on the serializer to enable configuration
link. Configuration link is active until the video link is
enabled. The video link overrides the configuration link
and attempts to lock when SEREN = 1.
Link Startup Procedure
Table 10 lists the start-up procedure for video-display
applications. Table 11 lists the startup procedure for
image-sensing applications. The control channel is avail-
able after the video link or the configuration link is estab-
lished. If the deserializer powers up after the serializer,
the control channel becomes unavailable until 2ms after
power-up.
Applications Information
PRBS Test
The serializer includes a PRBS pattern generator that
works with bit-error verification in the deserializer. To run
the PRBS test, set PRBSEN = 1 (0x04, D5) in the deserial-
izer and then in the serializer. To exit the PRBS test, set
PRBSEN = 0 (0x04, D5) in the serializer.
Error Generator
The serializer contains an error generator that enables
repeatable testing of the error-detection/correction fea-
tures of the GMSL link. Register 0x11 stores the configu-
ration bits for the error generator. A FC sets the error-
generation rate, type of errors, and the total number of
errors. The error generator is off by default.
Dual C Control
Usually systems have one FC to run the control channel,
located on the serializer side for video-display appli-
cations or on the deserializer side for image-sensing
applications. However, a FC can reside on each side
simultaneously and trade off running the control channel.
In this case, each FC can communicate with the serializer
and deserializer and any peripheral devices.
Contention occurs if both FCs attempt to use the control
channel at the same time. It is up to the user to prevent
this contention by implementing a higher-level protocol.
In addition, the control channel does not provide arbitra-
tion between I2C masters on both sides of the link. An
acknowledge frame is not generated when communica-
tion fails due to contention. If communication across the
serial link is not required, the FCs can disable the forward
and reverse control channel using the FWDCCEN and
REVCCEN bits (0x04, D[1:0]) in the serializer/deserial-
izer. Communication across the serial link is stopped and
contention between FCs cannot occur.
As an example of dual FC use in an image-sensing appli-
cation, the serializer can be in sleep mode, waiting for
wake-up by the FC on the deserializer side. After wake-
up, the serializer-side FC assumes master control of the
serializer’s registers.
Jitter-Filtering PLL
In some applications, the clock input (PCLKIN) includes
noise, which reduces link reliability. The clock input has a
programmable narrowband jitter-filter PLL that attenuates
frequencies higher than 100kHz (typ). Enable the jitter-
filter by setting ENJITFILT = 1 (0x05, D6).
PCLKIN Spread Tracking
The serializer can operate with a spread PCLKIN signal.
When using a spread PCLKIN signal, disable the jitter-
filter by setting ENJITFILT = 0 (0x05, D6). Do not exceed
the spread limitations in Table 7 and keep modulation
less than 40kHz. In addition, turn off spread spectrum
in the serializer/deserializer. The serializer/deserializer
track the spread on PCLKIN.
Changing the Clock Frequency
It is recommended that the serial link be enabled after
the video clock (fPCLKIN) and the control-channel clock
(fUART/fI2C) are stable. When changing clock frequency,
stop the video clock for 5Fs, apply the clock at the new
frequency, then restart the serial link or toggle SEREN.
On-the-fly changes in clock frequency are possible if
the new frequency is immediately stable and without
glitches. The reverse control channel remains unavail-
able for 350Fs after serial link start or stop. When using
the UART interface, limit on-the-fly changes in fUART to
factors of less than 3.5 at a time to ensure that the device
recognizes the UART sync pattern. For example, when
lowering the UART frequency from 1Mbps to 100kbps,
first send data at 333kbps, then at 100kbps for reduction
ratios of 3 and 3.333, respectively.
Fast Detection of Loss-of-Synchronization
A measure of link quality is the recovery time from loss-of-
synchronization. The host can be quickly notified of loss-
of-lock by connecting the deserializer’s LOCK output to
the deserializer’s GPI input. If LOCK is lost, GPO on the
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