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參數(shù)資料
| 型號： | MAX9273GTL/V+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 17/49頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SERIALIZER 22BIT GMSL 40TQFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | * |
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MAX9273
22-Bit GMSL Serializer with Coax or
STP Cable Drive
24
Maxim Integrated
The deserializer uses differential line coding to send
signals over the reverse channel to the serializer. The
bit rate of the control channel is 9.6kbps to 1Mbps in
both directions. The serializer/deserializer automatically
detect the control-channel bit rate in base mode. Packet
bit-rate changes can be made in steps of up to 3.5
times higher or lower than the previous bit rate. See the
Changing the Clock Frequency section for more informa-
tion on changing the control-channel bit rate.
Figure 21 detail the formats of the SYNC byte (0x79)
and the ACK byte (0xC3). The FC and the connected
slave chip generate the SYNC byte and ACK byte,
respectively. Events such as device wake-up and GPI
generate transitions on the control channel that can be
ignored by the FC. Data written to the serializer/deserial-
izer registers do not take effect until after the acknowl-
edge byte is sent. This allows the FC to verify that write
commands are received without error, even if the result
of the write command directly affects the serial link. The
slave uses the SYNC byte to synchronize with the host
UART’s data rate. If the GPI or MS/HVEN inputs of the
deserializer toggle while there is control-channel com-
munication, or if a line fault occurs, the control-channel
communication is corrupted. In the event of a missed
or delayed acknowledge (~1ms due to control-channel
timeout), the FC should assume there was an error in the
packet when the slave device received it, or that an error
occurred during the response from the slave device. In
base mode, the FC must keep the UART Tx/Rx lines high
for 16 bit times before starting to send a new packet.
Figure 17. Serial-Data Format
Table 3. Data-Rate Selection Table
DRS SETTING
DBL SETTING
BWS SETTING
PCLKIN RANGE (MHz)
0
0 (single input)
0 (24-bit mode)
16.66 to 50
0
1 (32-bit mode)
12.5 to 35
0
1 (double input)
0
33.3 to 100
0
1
25 to 75
1
0
8.33 to 16.66
1
0
1
6.25 to 12.5
1
0
Do not use
1
Do not use
D0
D1
D21
FCC
PCB
D0
D1
D29
FCC
PCB
FORWARD
CONTROL-
CHANNEL BIT
PACKET
PARITY
CHECK BIT
NOTE: SERIAL DATA SHOWN BEFORE SCRAMBLING AND 8b/10b ENCODING
VIDEO AND ERROR-
CORRECTION DATA
24 BITS
32 BITS
FORWARD
CONTROL-
CHANNEL BIT
PACKET
PARITY
CHECK BIT
VIDEO AND ERROR-
CORRECTION DATA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX9273GTL+T | IC SERIALIZER 22BIT GMSL 40TQFN |
| MAX9271GTJ/V+T | IC SERIALIZER 16BIT GMSL 32TQFN |
| VI-B3V-CU-S | CONVERTER MOD DC/DC 5.8V 200W |
| MAX9271GTJ+T | IC SERIALIZER 16BIT GMSL 32TQFN |
| VI-B3T-CU-S | CONVERTER MOD DC/DC 6.5V 200W |
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