參數(shù)資料
型號(hào): MAX9157EHJ+T
廠(chǎng)商: Maxim Integrated Products
文件頁(yè)數(shù): 2/16頁(yè)
文件大?。?/td> 0K
描述: IC TXRX QUAD LVDS 32-TQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類(lèi)型: 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 4/4
規(guī)程: LVDS
電源電壓: 3 V ~ 3.6 V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 32-TQFP
供應(yīng)商設(shè)備封裝: 32-TQFP(5x5)
包裝: 帶卷 (TR)
MAX9157
matching the differential impedance of the bus (taking
into account any reduced impedance due to loading).
Traces, Cables, and Connectors
The characteristics of input and output connections
affect the performance of the MAX9157. Use con-
trolled-impedance traces, cables, and connectors with
matched characteristic impedance.
Ensure that noise couples as common mode by run-
ning the traces of a differential pair close together.
Reduce within-pair skew by matching the electrical
length of the traces of a differential pair. Excessive
skew can result in a degradation of magnetic field can-
cellation. Maintain the distance between traces of a dif-
ferential pair to avoid discontinuities in differential
impedance. Minimize the number of vias to further pre-
vent impedance discontinuities.
Avoid the use of unbalanced cables, such as ribbon
cable. Balanced cables, such as twisted pair, offer
superior signal quality and tend to generate less EMI
due to canceling effects. Balanced cables tend to pick
up noise as common mode, which is rejected by the
receiver.
Board Layout
A four-layer PC board that provides separate power,
ground, input, and output signals is recommended.
Keep the LVTTL/LVCMOS and BLVDS signals separat-
ed to prevent coupling.
Quad Bus LVDS Transceiver
10
______________________________________________________________________________________
INPUTS
OUTPUTS
RE_
VID = (VDO_+/RIN_+) - (VDO_-/RIN_-)
RO_
LVID < -100mV
L
LVID > 100mV
H
L
Fail-safe operation guaranteed when
DO_+/RIN_+ and DO_-/RIN_- are
open, undriven and shorted, or
undriven and parallel terminated
H
HX
Z
Table 3. Receiver Mode
PIN
INTERNAL RESISTOR
DE12
Pulldown to GND
DE34
Pulldown to GND
RE12
Pullup to VCC
RE34
Pullup to VCC
DIN_
Pullup to VCC
Table 4. Input Internal Pullup/Pulldown
Resistors
RL
CL
DO_+/RIN_+
DO_-/RIN_-
CL
50
DIN_
GENERATOR
Figure 3. Driver Propagation Delay and Transition Time Test Circuit
V OS
VCC
GND
DIN_
RL/2
VOS
VOD
DO_-/RIN_-
D0_+/RIN_+
Figure 2. Driver VOD and VOS Test Circuit
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