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參數(shù)資料
| 型號： | MAX9157EHJ+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 16/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX QUAD LVDS 32-TQFP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 4/4 |
| 規(guī)程： | LVDS |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP |
| 供應商設備封裝： | 32-TQFP（5x5） |
| 包裝： | 帶卷 (TR) |
a driver located on a card in the middle of the bus is
27
because the driver sees two 54 loads in parallel.
A typical LVDS driver (rated for a 100
load) would not
develop a large enough differential signal to be reliably
detected by an LVDS receiver. The MAX9157 BLVDS
drivers are designed and specified to drive a 27
load
to differential voltage levels of 250mV to 460mV. A stan-
dard LVDS receiver is able to detect this level of differ-
ential signal. Short extensions off the bus, called stubs,
contribute to capacitive loading. Keep stubs less than
1in for a good balance between ease of component
placement and good signal integrity.
The MAX9157 driver outputs are current-source drivers
and drive larger differential signal levels into loads
lighter than 27
and smaller levels into loads heavier
than 27
(see Typical Operating Characteristics
curves). To keep loading from reducing bus impedance
below the rated 27
load, PC board traces can be
designed for higher unloaded characteristic impedance.
Effect of Transition Times
For transition times (measured from 0% to 100%) short-
er than the delay between capacitive loads, the loads
are seen as low-impedance discontinuities from which
the driven signal is reflected. Reflections add and sub-
tract from the signal being driven and cause decreased
noise margin and jitter. The MAX9157 output drivers
are designed for a minimum transition time of 1ns
(rated 0.6ns from 20% to 80%, or about 1ns from 0% to
100%) to reduce reflections while being fast enough for
high-speed backplane data transmission.
Power-On Reset
The power-on reset voltage of the MAX9157 is typically
2.25V. When the supply falls below this voltage, the
devices are disabled and the receiver inputs/driver out-
puts are in high impedance. The power-on reset
ensures glitch-free power-up and power-down, allow-
ing hot swapping of cards in a multicard bus system
without disrupting communications.
Receiver Input Hysteresis
The MAX9157 receiver inputs feature 52mV hysteresis to
increase noise immunity for low-differential input signals.
Operating Modes
The MAX9157 features driver/receiver enable inputs
that select the bus I/O function (Table 1). Tables 2 and
3 show the driver and receiver truth tables.
Input Internal Pullup/Pulldown
Resistors
The MAX9157 includes pullup or pulldown resistors
(300k
) to ensure that unconnected inputs are defined
(Table 4).
Applications Information
Supply Bypassing
Bypass each supply pin with high-frequency surface-
mount ceramic 0.1F and 1nF capacitors in parallel as
close to the device as possible, with the smaller value
capacitor closest to the device.
Termination
In the example given in the Effect of Capacitive Loading
section, the loaded differential impedance of a bus is
reduced to 54
. Since the bus can be driven from any
card position, the bus must be terminated at each end. A
parallel termination of 54
at each end of the bus placed
across the traces that make up the differential pair pro-
vides a proper termination. The total load seen by the dri-
ver is 27
. The MAX9157 drives higher differential signal
levels into lighter loads. (See Differential Output Voltage
vs. Output Load graph in the Typical Operating Char-
acteristics section). A multidrop bus with the driver at one
end and receivers connected at regular intervals along
the bus has a lowered impedance due to capacitive load-
ing. Assuming a 54
impedance, the multidrop bus can
be terminated with a single, parallel-connected 54
resis-
tor at the far end from the driver. Only a single resistor is
required because the driver sees one 54
differential
trace. The signal swing is larger with a 54
load. In gen-
eral, parallel terminate each end of the bus with a resistor
MAX9157
Quad Bus LVDS Transceiver
_______________________________________________________________________________________
9
MODE SELECTED
DE_
RE_
Driver Mode
H
Receiver Mode
L
High-Impedance Mode
L
H
Loopback Mode
H
L
Table 1. I/O Enable Functional Table
INPUTS
OUTPUTS
DE_
DIN_
DO_+/RIN_+
DO_-/RIN_-
HL
L
H
HH
H
L
LX
Z
Table 2. Driver Mode
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9158 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Quad Bus LVDS Transceiver in 44 QFN |
| MAX9158EGM | 制造商:Maxim Integrated Products 功能描述:QUAD BUS LVDS TRANSCEIVER IN 44-PIN QFN - Rail/Tube 制造商:Rochester Electronics LLC 功能描述: |
| MAX9158EGM-T | 制造商:Maxim Integrated Products 功能描述:QUAD BUS LVDS TRANSCEIVER IN 44-PIN QFN - Tape and Reel |
| MAX9159 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Dual LVDS Line Receiver |
| MAX9159ESA | 制造商:Maxim Integrated Products 功能描述:DUAL LVDS LINE RECEIVER - Rail/Tube |
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