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M
Constant-Frequency, Half-Bridge CCFL
Inverter Controller
24
______________________________________________________________________________________
Parallel capacitor C3 sets the maximum operating fre-
quency, which is also the parallel-resonant peak fre-
quency. Choose:
In the circuit of Figure 1, the maximum resonant fre-
quency is 70kHz, C1 and C2 are 2.2μF, and the sec-
ondary leakage inductance is 300mH. Therefore, use a
capacitor of 12pF or greater for C3.
The transformer core saturation should also be consid-
ered when selecting the operating frequency. The pri-
mary winding should have enough turns to prevent
transformer saturation under all operating conditions.
Use the following expression to calculate the minimum
number of turns N1 of the primary winding:
where D
MAX
is the maximum duty cycle (approximately
0.8) of the high-side switch, V
IN(MAX)
is the maximum
DC input voltage, B
S
is the saturation flux density of the
core, and A is the minimal cross-section area of the core.
COMP Capacitor Selection
The COMP capacitor sets the speed of the current-reg-
ulation loop that is used during startup, maintaining
lamp-current regulation, and during transients caused
by changing the input voltage. To maintain stable oper-
ation, the COMP capacitor (C
COMP
) needs to be at
least 3.3nF.
As discussed in the
Digital PWM Dimming Control
sec-
tion, the COMP capacitor also limits the dynamics of
the lamp-current envelope in digital PWM operation. At
the end of the digital PWM ON cycle, the MAX8729
turns on a 100μA internal current source to linearly dis-
charge the COMP capacitor. Use the following equa-
tion to set the fall time:
where t
FALL
is the fall time of the lamp-current envelope
and 1.5V is the dynamic range of the COMP voltage. At
the beginning of the digital PWM ON cycle, the COMP
capacitor is charged by transconductance error ampli-
fier, so the charge current is not constant. Because the
average charge current is around 30μA, the rise time is
about three times longer than the fall time.
Setting the Fault-Delay Time
The TFLT capacitor determines the delay time for both
the open-lamp fault and secondary short-circuit fault.
The MAX8729 charges the TFLT capacitor with a 1μA
current source during an open-lamp fault and charges
the TFLT capacitor with a 126μA current source during
a secondary short-circuit fault. Therefore, the sec-
ondary short-circuit fault-delay time is approximately
100 times shorter than that of the pen-lamp fault. The
MAX8729 sets the fault latch when the TFLT voltage
reaches 4V. Use the following equations to calculate
the open-lamp fault delay (T
OPEN_LAMP
) and sec-
ondary short-circuit fault delay (T
SEC_SHORT
):
Bootstrap Capacitor
The high-side gate driver is powered using a bootstrap
circuit. The MAX8729 integrates the bootstrap diode so
only one 0.1μF bootstrap capacitor is needed. Connect
the capacitor between LX and BST to complete the
bootstrap circuit.
Layout Guidelines
Careful PC board layout is important to achieve stable
operation. The high-voltage section and the switching
section of the circuit require particular attention. The
high-voltage sections of the layout need to be well sep-
arated from the control circuit. Follow these guidelines
for good PC board layout:
1) Keep the high-current paths short and wide, espe-
cially at the ground terminals. This is essential for
stable, jitter-free operation and high efficiency.
2) Use a star-ground configuration for power and ana-
log grounds. The power and analog grounds
should be completely isolated—meeting only at the
center of the star. The center should be placed at
the analog ground pin (GND). Using separate cop-
per islands for these grounds can simplify this task.
Quiet analog ground is used for V
CC
, COMP, HF,
LF, and TFLT.
T
C
x V
A
x V
A
μ
T
C
OPEN LAMP
_
TFLT
1
SEC SHORT
_
TFLT
126
=
μ
=
4
4
C
A x t
μ
1 5
V
COMP
FALL
=
100
N
D
x V
B x A x f
MAX
IN MAX
(
MIN
1
>
)
C
C
C
x f
x Lx C
N
MAX
S
3
1
2
4
2
2
2
≤
+
π