
M
Constant-Frequency, Half-Bridge CCFL
Inverter Controller
14
______________________________________________________________________________________
Detailed Description
Figure 1 shows the Stand-Alone Typical Operating
Circuit. Figure 2 shows the Functional Diagram of the
MAX8729. The circuit architecture consists of a half-
bridge inverter, which converts unregulated DC into a
nearly sinusoidal, high-frequency, AC output for power-
ing CCFLs. The MAX8729 is biased from an internal
5.35V linear regulator with UVLO comparator that
ensures stable operation and clean startup characteris-
tics. There are several layers of fault-protection circuit-
ry, consisting of comparators for detecting primary-side
current limit, secondary-side overvoltage, secondary
short circuit, and open-lamp faults. A logic block arbi-
trates the comparator outputs by making sure that a
given fault persists for a minimum duration before reg-
istering the fault condition. A separate block provides
dimming control based upon analog or DPWM inputs.
Finally, a dedicated logic circuit provides synchroniza-
tion and phase control functions for daisy chaining up
to five MAX8729s without phase overlap.
The inverter operates in resonant mode during striking
and switches over to constant-frequency operation
after all the lamps are lit. This unique feature ensures
reliable striking under all conditions and reduces the
transformer stress. The constant-frequency architecture
can be synchronized and phase shifted for daisy-
chained applications. Multiple lamps can also be dri-
ven in parallel within a single stage. The MAX8729’s
gate drivers are strong enough to drive the large-power
MOSFETs needed when one power stage drives four or
more CCFL lamps in parallel.
The MAX8729 provides accurate lamp-current regulation
(±2.5%). A primary-side current sense provides cycle-
by-cycle current limit and zero-crossing detection, while
the secondary current is sensed with a separate loop
that provides fine adjustment of the lamp current with an
external resistor. The MAX8729 controls lamp brightness
by turning the CCFL on and off using a DPWM method,
while maintaining approximately constant lamp current.
The brightness set point can be adjusted with an analog
voltage on the CNTL pin, or with an external PWM signal.
The MAX8729 has a single compensation input
(COMP), which also establishes the soft-start and soft-
stop timing characteristics. Control logic changes the
available drive current at COMP based on the operat-
ing mode to adjust the inverter’s dynamic behavior.
Constant-Frequency Operation
The MAX8729 operates in constant-frequency mode in
normal operation. There are two ways to set the switch-
ing frequency:
1)
The switching frequency can be set with an external
resistor connected between HF and GND. The switch-
ing frequency is given by the following equation:
The adjustable range of the switching frequency is
between 20kHz and 100kHz (R
HF
is between 270k
Ω
and 54k
Ω
).
2)
The switching frequency can be synchronized by
an external high-frequency signal. Connect HF to
GND through a 100k
Ω
resistor, and connect
HSYNC to the external high-frequency signal. The
resulting synchronized switching frequency (f
SW
) is
1/6th the frequency of the external signal (f
EXT
):
The frequency range of the external signal should be
between 190kHz and 460kHz, with R
HF
+ 100k
Ω
result-
ing in a switching frequency range between 32kHz and
77kHz.
Figure 3 illustrates the constant-frequency operation,
with timing diagrams that show the primary current,
clock signal, and gate-drive signals. At the beginning
of the positive half cycle, the high-side switch is on and
the primary current ramps up. The controller turns off
the high-side switch at t
1
. The primary current contin-
ues to flow in the same direction, which forward biases
the body diode of the low-side switch after the high-
side switch is off. When the controller turns on the low-
side switch, the voltage drop across the switch is
nearly zero. This zero-voltage switching (ZVS) opera-
tion results in lower switching losses. With DL on, the
primary current ramps down. If the primary current
reaches zero (t
2
) before the falling edge of the oscilla-
tor clock arrives (t
3
), as shown in Figure 3(A), the con-
troller turns off the low-side switch at t
2
. Both the
high-side switch and low-side switch stay off until t
3
.
The controller turns on the low-side switch at the falling
edge of the clock (t
3
). The primary current ramps up in
the other direction, starting the negative half cycle. If
the clock falling edge comes before the zero crossing
as shown in Figure 3(B), the low-side switch stays on,
which allows the primary current to reach zero and then
f
f
SW
EXT
6
=
f
kHz x
k
R
SW
HF
=
Ω
54
100