參數(shù)資料
型號: MAX8722EEG
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 穩(wěn)壓器
英文描述: Low-Cost CCFL Backlight Controller
中文描述: FLUORESCENT LIGHT CONTROLLER, PDSO24
封裝: 0.150 INCH, 0.250 INCH PITCH, MO-137AE, QSOP-24
文件頁數(shù): 9/20頁
文件大?。?/td> 331K
代理商: MAX8722EEG
M
Low-Cost CCFL Bac klight Controller
_______________________________________________________________________________________
9
PIN
NAME
FUNCTION
1
BATT
Supply Input. BATT is the input to the internal 5.4V linear regulator that powers the device. Bypass BATT to
GND with a 0.1μF ceramic capacitor.
Shutdown Control Input. The device shuts down when
SHDN
is pulled to GND.
Primary Current-Limit Adjustment Input. Connect a resistive voltage-divider between V
CC
and GND to set
the primary current limit. The current-limit threshold is 1/5 of the voltage at ILIM. Connect it to V
CC
with a
pullup resistor to select the default current-limit threshold of 0.2V.
Fault Timer Adjustment Pin. Connect a capacitor from TFLT to GND to set the timeout periods for open-
lamp and secondary overcurrent faults.
2
SHDN
3
ILIM
4
TFLT
5
CNTL
Brightness Control Input. Varying V
CNTL
between 0 and 2V varies the DPWM duty cycle (brightness)
between 10% (minimum) and 100% (maximum). The brightness remains at maximum for V
CNTL
greater
than 2V.
Dual-Function DPWM Signal Pin. The DPWM pin can be used either as the DPWM signal output or as a
low-frequency sync input. See the
Digital PWM Dimming Control
and
Digital PWM Frequency Setting
sections.
DPWM High-Frequency Sync Input. The DPWM chopping frequency can be synchronized to an external
high-frequency signal by connecting FREQ to V
CC
and SYNC to the external signal source. The DPWM
chopping frequency is 1/128 of the frequency of the external signal.
DPWM Frequency Dual-Mode Adjustment Pin. Connect a resistor from FREQ to GND to set the DPWM
frequency. Connect FREQ to V
CC
to set DPWM frequency using SYNC.
f
DPWM
= 209Hz x 169k
/ R
FREQ
Transconductance Error-Amplifier Output. A compensation capacitor connected between COMP and GND
sets the rise and fall time of the lamp current in DPWM operation.
Lamp-Current Feedback Input. The average voltage on IFB is regulated to 0.8V by controlling the on-time
of high-side switches. If V
IFB
falls below 0.6V for a period longer than the timeout period set by TFLT, the
MAX8722 activates the fault latch.
Transformer Secondary Voltage Feedback Input. A capacitive voltage-divider between the high-voltage
terminal of the CCFL tube and GND sets the maximum average lamp voltage during lamp strike and open-
lamp conditions. When the average voltage on VFB exceeds the internal overvoltage threshold, the
controller turns on an internal current sink discharging the COMP capacitor.
Transformer Secondary Current Feedback Input. A current-sense resistor connected between the low-
voltage end of the transformer secondary and ground sets the maximum secondary current during faults.
When the average voltage on ISEC exceeds the internal overcurrent threshold, the controller turns on an
internal current sink discharging the COMP capacitor.
High-Side MOSFET NH2 Gate-Driver Output
GH2 Gate-Driver Return. LX2 is the input to the current-limit and zero-crossing comparators. The device
senses the voltage across the low-side MOSFET NL2 to detect primary current zero-crossing and primary
overcurrent.
GH2 Gate-Driver Supply Input. Connect a 0.1μF capacitor from LX2 to BST2 and a diode from V
DD
to BST2
to form a bootstrap circuit.
GH1 Gate-Driver Supply Input. Connect a 0.1μF capacitor from LX1 to BST1 and a diode from V
DD
to BST1
to form a bootstrap circuit.
GH1 Gate-Driver Return. LX1 is the input to the current-limit and zero-crossing comparators. The device
senses the voltage across the low-side MOSFET NL1 to detect primary current zero-crossing and primary
overcurrent.
6
DPWM
7
SYNC
8
FREQ
9
COMP
10
IFB
11
VFB
12
ISEC
13
GH2
14
LX2
15
BST2
16
BST1
17
LX1
Pin Desc ription
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