參數(shù)資料
型號(hào): MAX8722EEG
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 穩(wěn)壓器
英文描述: Low-Cost CCFL Backlight Controller
中文描述: FLUORESCENT LIGHT CONTROLLER, PDSO24
封裝: 0.150 INCH, 0.250 INCH PITCH, MO-137AE, QSOP-24
文件頁數(shù): 16/20頁
文件大?。?/td> 331K
代理商: MAX8722EEG
M
In digital PWM operation, COMP controls the rise and
fall time of the lamp-current envelope. At the beginning
of the digital PWM on-cycle, V
COMP
rises linearly, grad-
ually increasing t
ON
, which provides soft-start. At the
end of the digital PWM on-cycle, the COMP capacitor
discharges linearly, gradually decreasing t
ON
and pro-
viding soft-stop.
Digital PWM Frequenc y S etting
There are three ways to set the digital PWM frequency.
1) The digital PWM frequency can be set with an
external resistor. Connect SYNC to GND and con-
nect a resistor between FREQ and GND. The digital
PWM frequency is given by the following equation:
The adjustable range of the digital PWM frequency
is between 100Hz and 350Hz (R
FREQ
is between
353k
and 101k
). CNTL controls the digital PWM
duty cycle.
2) The digital PWM frequency can be clocked by an
external high-frequency signal. Connect FREQ to
V
CC
and connect SYNC to the external high-fre-
quency signal. The digital PWM frequency is 1/128
of the frequency of the external signal:
where f
EXT
is the frequency of the external signal.
The frequency range of the external signal should
be between 13kHz and 45kHz, resulting in a digital
PWM frequency range between 100Hz and 350Hz.
CNTL controls the DPWM duty cycle.
3) The digital PWM frequency can be synchronized to
an external low-frequency signal. To enable this
mode, connect SYNC to V
CC
, connect FREQ to
GND through a 100k
resistor, and connect DPWM
to the external low-frequency signal. The digital
PWM frequency and duty cycle are equal to those
of the external signal.
The frequency range of the external signal is between
100Hz and 350Hz. In this mode, the brightness control
input CNTL is disabled, and the brightness is propor-
tional to the duty cycle of the external signal.
Table 3 summarizes the three ways of setting the digital
PWM frequency.
UV LO
The MAX8722 includes an undervoltage-lockout
(UVLO) circuit. The UVLO circuit monitors the V
CC
volt-
age. When V
CC
is below 4.2V (typ), the MAX8722 dis-
ables both high-side and low-side MOSFET drivers and
resets the fault latch.
Low-Power S hutdown
When the MAX8722 is placed in shutdown, all functions
of the IC are turned off except for the 5.4V linear regu-
lator. In shutdown, the linear-regulator output voltage
drops to about 4.5V and the supply current is 6μA (typ).
While in shutdown, the fault latch is reset. The device
can be placed into shutdown by pulling
SHDN
to its
logic-low level.
Lamp-Out Protec tion
For safety, the MAX8722 monitors the lamp-current
feedback (IFB) to detect faulty or open CCFL tubes and
secondary short circuits in the lamp and IFB sense
resistor. As described in the
Lamp-Current Regulation
section, the voltage on IFB is internally full-wave recti-
fied. If the rectified IFB voltage is below 600mV, the
MAX8722 charges the TFLT capacitor with 1μA. The
f
f
128
DPWM
EXT
=
f
DPWM
Hz
k
R
FREQ
×
/
=
209
169
Low-Cost CCFL Bac klight Controller
16
______________________________________________________________________________________
FREQ
SYNC
DPWM
DIGITAL PWM
FREQUENCY/DUTY CYCLE
Connect FREQ to GND
through an external resistor.
Connect SYNC to GND.
DPWM is used as the digital PWM
signal output.
The resistor value sets the frequency.
CNTL controls the duty cycle.
Connect FREQ to V
CC
.
Connect SYNC to an
external high-frequency
signal.
DPWM is used as the digital PWM
signal output.
The frequency is 1/128 of the
frequency of the external signal. CNTL
controls the duty cycle.
Connect FREQ to GND
through a 100k
resistor.
Connect SYNC to V
CC
.
Connect DPWM to an external
low-frequency signal.
The frequency and duty cycle are
equal to those of the external signal.
Table 3. Digital PWM Frequency Setting
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