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參數(shù)資料
| 型號： | MAX8632 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Quadruple 2-Input Positive-NAND Gates With Open-Drain Outputs 20-LCCC -55 to 125 |
| 中文描述： | 集成DDR電源方案，適用于臺式機(jī)、筆記本電腦和圖形卡 |
| 文件頁數(shù)： | 22/29頁 |
| 文件大小： | 512K |
| 代理商： | MAX8632 |
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M
where V
GS
= V
DD
= 5V. In addition to the losses above,
allow about 20% more for additional losses because of
MOSFET output capacitances and low-side MOSFET
body-diode reverse-recovery charge dissipated in the
high-side MOSFET that is not well defined in the
MOSFET data sheet. Refer to the MOSFET data sheet
for thermal-resistance specifications to calculate the PC
board area needed to maintain the desired maximum
operating junction temperature with the above-calculat-
ed power dissipations. To reduce EMI caused by
switching noise, add a 0.1μF ceramic capacitor from the
high-side switch drain to the low-side switch source, or
add resistors in series with DH and DL to slow down the
switching transitions. Adding series resistors increases
the power dissipation of the MOSFET, so ensure that
this does not overheat the MOSFET.
MOSFET Snubber Circuit (Buck)
Fast switching transitions cause ringing because of a
resonating circuit formed by the parasitic inductance
and capacitance at the switching nodes. This high-fre-
quency ringing occurs at LX’s rising and falling transi-
tions and can interfere with circuit performance and
generate EMI. To dampen this ringing, an optional
series RC snubber circuit is added across each switch.
Below is a simple procedure for selecting the value of
the series RC of the snubber circuit:
1) Connect a scope probe to measure V
LX
to PGND1,
and observe the ringing frequency, f
R
.
2) Estimate the circuit parasitic capacitance (C
PAR
) at
LX by first finding a capacitor value, which, when
connected from LX to PGND1, reduces the ringing
frequency by half. C
PAR
can then be calculated as
1/3rd the value of the capacitor value found.
3) Estimate the circuit parasitic inductance (L
PAR
) from
the equation:
4) Calculate the resistor for critical dampening (R
SNUB
)
from the equation: R
SNUB
= 2
π ×
f
R
x L
PAR
. Adjust
the resistor value up or down to tailor the desired
damping and the peak voltage excursion.
5) The capacitor (C
SNUB
) should be at least 2 to 4
times the value of C
PAR
to be effective.
The power loss of the snubber circuit (P
RSNUB
) is dissi-
pated in the resistor and can be calculated as:
where V
IN
is the input voltage and f
SW
is the switching
frequency. Choose an R
SNUB
power rating that meets
the specific application’s derating rule for the power
dissipation calculated.
Setting the Current Limit (Buck)
The current-sense method used in the MAX8632 makes
use of the on-resistance (R
DS(ON)
) of the low-side
MOSFET (Q2 in the Typical Applications Circuit of Figure
8). When calculating the current limit, use the worst-case
maximum value for R
DS(ON)
from the MOSFET data
sheet, and add some margin for the rise in R
DS(ON)
with
temperature. A good general rule is to allow 0.5% addi-
tional resistance for each 1°C of temperature rise.
The minimum current-limit threshold must be great
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The val-
ley of the inductor current occurs at I
LOAD(MAX)
minus
half the ripple current; therefore:
where I
LIM(VAL)
equals the minimum valley current-limit
threshold voltage divided by the on-resistance of Q2
(R
DS(ON)Q2
). For the 50mV default setting, connect ILIM
to AV
DD
. In adjustable mode, the valley current-limit
threshold is precisely 1/10th* the voltage seen at ILIM.
For an adjustable threshold, connect a resistive divider
from REF to GND with ILIM connected to the center tap.
The external 250mV to 2V adjustment range corresponds
to a 25mV to 200mV valley current-limit threshold. When
adjusting the current limit, use 1% tolerance resistors and
a divider current of approximately 10μA to prevent signifi-
cant inaccuracy in the valley current-limit tolerance.
Foldback Current Limit
Alternately, foldback current limit can be implemented
if the UVP latch option is not available. Foldback cur-
rent limit reduces the power dissipation of external
components so they can withstand indefinite overload
and short circuit, with automatic recovery after the over-
load or short circuit is removed. To implement foldback
current limit, connect a resistor from V
OUT
to ILIM (R6
in Figure 7 and in the Typical Applications Circuit of
Figure 8), in addition to the resistor-divider network (R4
I
I
I
LIR
LIM VAL
(
LOAD MAX
LOAD MAX
)
(
)
(
)
-
>
×
2
P
C
V
f
RSNUB
SNUB
IN
SW
=
×
×
2
L
f
C
PAR
R
PAR
=
×
(
)
×
1
2
2
π
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
22
______________________________________________________________________________________
*
In the negative direction, the adjustable current limit is typically
-1/8th the voltage seen at ILIM.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX8632ETI+ | 功能描述:PMIC 解決方案 DDR Power-Supply Solution RoHS:否 制造商:Texas Instruments 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-24 封裝:Reel |
| MAX8632ETI+T | 功能描述:PMIC 解決方案 DDR Power-Supply Solution RoHS:否 制造商:Texas Instruments 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-24 封裝:Reel |
| MAX8632ETI+TGD2 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| MAX8632EVKIT | 功能描述:電源管理IC開發(fā)工具 RoHS:否 制造商:Maxim Integrated 產(chǎn)品:Evaluation Kits 類型:Battery Management 工具用于評估:MAX17710GB 輸入電壓: 輸出電壓:1.8 V |
| MAX8633ELA+ | 制造商:Maxim Integrated Products 功能描述: |
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