參數(shù)資料
型號: MAX8632
廠商: Maxim Integrated Products, Inc.
英文描述: Quadruple 2-Input Positive-NAND Gates With Open-Drain Outputs 20-LCCC -55 to 125
中文描述: 集成DDR電源方案,適用于臺式機(jī)、筆記本電腦和圖形卡
文件頁數(shù): 21/29頁
文件大?。?/td> 512K
代理商: MAX8632
capacitor. Nevertheless, a ceramic capacitor of at least
10μF must be used and must be added and placed as
close as possible to the VTTI pin. This value must be
increased with larger load current, or if the trace from
the VTTI pin to the power source is long and has signifi-
cant impedance. Furthermore, to prevent undesirable
VTTI bounce from coupling back to the REFIN input
and possibly causing instability in the loop, the REFIN
pin should ideally tap its signal from a separate low-
impedance DC source rather than directly from the
VTTI input. If the latter is unavoidable, increase the
amount of bypass capacitance at the VTTI input and
add additional bypass at the REFIN pin.
MOSFET Selection (Buck)
The MAX8632 drives external, logic-level, n-channel
MOSFETs as the circuit-switch elements. The key
selection parameters:
On-resistance (R
DS(ON)
):
the lower, the better.
Maximum drain-to-source voltage (V
DSS
):
should be
at least 20% higher than input supply rail at the high-
side MOSFET’s drain.
Gate charges (Q
G
, Q
GD
, Q
GS
):
the lower the better.
Choose MOSFETs with rated R
DS(ON)
at V
GS
= 4.5V.
For a good compromise between efficiency and cost,
choose the high-side MOSFET that has a conduction
loss equal to its switching loss at nominal input voltage
and maximum output current (see below). For the low-
side MOSFET, make sure that it does not spuriously
turn on because of dV/dt caused by the high-side
MOSFET turning on, as this results in shoot-through
current degrading efficiency. MOSFETs with a lower
Q
GD
to Q
GS
ratio have higher immunity to dV/dt.
For proper thermal-management design, calculate the
power dissipation at the desired maximum operating
junction temperature, maximum output current, and
worst-case input voltage. For the low-side MOSFET, the
worst case is at V
IN(MAX)
. For the high-side MOSFET,
the worst case could be at either V
IN(MIN)
or V
IN(MAX)
.
The high-side MOSFET and low-side MOSFET have dif-
ferent loss components due to the circuit operation.
The low-side MOSFET operates as a zero-voltage
switch; therefore, major losses are:
The channel-conduction loss (P
LSCC
)
The body-diode conduction loss (P
LSDC
)
The gate-drive loss (P
LSDR
):
Use R
DS(ON)
at T
J(MAX)
:
where V
F
is the body-diode forward-voltage drop, t
DT
is
the dead time (
30ns), and f
SW
is the switching fre-
quency. Because of the zero-voltage switch operation,
the low-side MOSFET gate-drive loss occurs as a result
of charging and discharging the input capacitance,
(C
ISS
). This loss is distributed among the average DL
gate-driver’s pullup and pulldown resistance, R
DL
(
1
), and the internal gate resistance (R
GATE
) of the
MOSFET (
2
). The drive power dissipated is given by:
The high-side MOSFET operates as a duty-cycle control
switch and has the following major losses:
The channel-conduction loss (P
HSCC
)
The VI overlapping switching loss (P
HSSW
)
The drive loss (P
HSDR
)
(The high-side MOSFET does not have body-diode
conduction loss because the diode never conducts
current):
Use R
DS(ON)
at T
J(MAX)
:
where I
GATE
is the average DH-driver output current
determined by:
where R
DH
is the high-side MOSFET driver’s on-resis-
tance (1
typ) and R
GATE
is the internal gate resis-
tance of the MOSFET (
2
):
×
×
×
P
Q
V
f
R
R
R
HSDR
G
GS
SW
GATE
+
GATE
DH
=
.
(
)
I
V
R
R
GATE ON
DH
GATE
=
+
2 5
×
×
P
V
I
f
Q
Q
I
HSSW
IN
LOAD
SW
GS
GD
GATE
=
×
+
(
)
P
V
V
I
R
HSCC
OUT
IN
LOAD
DS ON
=
×
×
2
×
×
×
P
C
V
f
R
R
R
LSDR
ISS
GS
SW
GATE
+
GATE
DL
=
2
×
P
I
V
t
f
LSDC
LOAD
F
DT
SW
=
×
×
2
1
(
)
P
V
V
I
R
LSCC
OUT
IN
LOAD
DS ON
=
×
×
2
-
M
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
______________________________________________________________________________________
21
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