參數(shù)資料
型號： MAX7651CCB
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 模擬信號調(diào)理
英文描述： Flash Programmable 12-Bit Integrated Data-Acquisition Systems
中文描述： SPECIALTY ANALOG CIRCUIT, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, MO-136BJ, TQFP-64
文件頁數(shù)： 32/36頁
文件大小： 479K
代理商： MAX7651CCB
M
Flash Programmable 12-Bit Integrated
Data-Acquisition Systems
32
______________________________________________________________________________________
Power Requirements
MAX7651 operates from +5V while the MAX7652 oper-
ates from +3V analog and digital supply voltages. The
analog supply current is typically 2mA. The typical digi-
tal supply currents (continuous A/D conversions at
12MHz clock frequency) are 5mA and 13mA at +3V
and +5V, respectively. Current consumption will vary
depending on RAM read/write and flash read/write
page erase duty cycle.
Idle Mode
In idle mode, CPU processing is suspended and inter-
nal data registers maintain their current data. However,
unlike typical 8051 systems, the clock is not disabled
internally. Set PCON.0 (IDLE) high to enter the Idle
INTERRUPT
ASSOCIATED FEATURE
ENABLE SFR BIT
(NOTE 2)
PRIORITY SFR BIT
(NOTE 3)
PRIORITY
INT0
INT1
FLASH
ADC
WDTI
TF0 or EXF0
TF1 or EXF2
TI_0 or RI_0
TF2 or EXF2
TI_1 or RI_1
External Interrupt 0
External Interrupt 1
Flash Operation Complete
A / D Operation Complete
Watchdog Timer
Timer 0
Timer 1
Serial Port 0
Timer 2
Serial Port 1
IE.0
IE.2
EIE.0
EIE.1
EICON.1
IE.1
IE.3
IE.4
IE.5
IE.6
IP.0
IP.1
EIP.0
EIP.1
EIP.4
IP.1
IP.3
IP.4
IP.5
IP.6
1
3
8
9
10
2
4
5
6
7
Table 26. MAX7651/MAX7652 Interrupts (Note 1)
Note 1:
Shaded areas reflect the 8051 industry standard.
Note 2:
Set Enable SFR bit high to enable interrupt.
Note 3:
Set Priority SFR bit high to eatablish high priority.
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
WD1
WD0
TIMER2
TIMER1
TIMER0
MD2
MD1
MD0
BIT
7
6
NAME
WD1
WD10
DESCRIPTION
Set WD1 and WD0 to adjust the interrupt interval for the watchdog timer. (See
Watchdog Timer
.)
5
TIMER2
Timer 2 Control. Set TIMER2 = 1 for TIMER2-associated counter increments at four clock
intervals. Set TIMER2 = 0 for increments at 12 clock intervals.
4
TIMER1
Timer 1 Control. Set TIMER1 = 1 for Timer1-associated counter increments at four clock
intervals. Set TIMER1 = 0 for increments at 12 clock intervals.
3
TIMER0
Timer 0 Control. Set TIMER0 = 1 for Timer0-associated counter increments at four clock
intervals. Set TIMER0 = 0 for increments at 12 clock intervals.
2
1
0
MD2
MD1
MD0
Set MD2, MD1, and MD0 to adjust the Read/Write strobe width (in clocks). The number of clock
cycles is two plus the MD2, MD1, MD0 decimal value. MD0 is the LSB.
Table 27. CKCON SFR Address 8EH
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