參數(shù)資料
型號： MAX7651CCB
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 模擬信號調(diào)理
英文描述： Flash Programmable 12-Bit Integrated Data-Acquisition Systems
中文描述： SPECIALTY ANALOG CIRCUIT, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, MO-136BJ, TQFP-64
文件頁數(shù)： 30/36頁
文件大?。?/td> 479K
代理商： MAX7651CCB
M
Flash Programmable 12-Bit Integrated
Data-Acquisition Systems
30
______________________________________________________________________________________
External Flash Memory Mass Erase
A mass erase operation sets all bits, including the lock
bits to
“
1
”
(Table 22).
External Erase:
Both FLASH arrays can be simultaneously mass-erased
electrically by using the proper combination of control
signals as shown in Table 2. The erase operation must
be executed before either memory can be pro-
grammed. Lock bits are also erased (Set to 1).
External chip erase power-up sequence:
1) Power-up chip with RST asserted, and allow ALE
and
PSEN
to float to the
“
1
”
state (they will be inter-
nally pulled-up during RST assertion). Wait 10ms for
the internal bandgap and oscillator to stabilize.
2) Pull
PSEN
LOW,
EA
HIGH, set P2.6, P2.7, P3.6,
P3.7, and P2.5, as per Mass Erase mode in the
Flash Programming Modes (table 2).
3) P3.4 will be LOW during mass erase cycle and
return HI at the end of mass erase cycle.
External chip erase power-down sequence:
1) Power-down sequence
A)Remove drive from and allow
PSEN
and ALE/
PROG
to float high.
B) Pull
EA
low.
C) Hi - z all digital pins.
D) Remove power from all power pins.
Figure 2 shows the timing waveforms that apply for the
Flash memory mass erase operation.
Flash Memory Lock Bits
The MAX7651/MAX7652 each contains three lock bits
which can be left unprogrammed (logic
“
1
”
) or can be
programmed (logic
“
0
”
) to obtain the additional fea-
tures listed in the table below:
When lock bit
“
1
”
is programmed (set to logic
“
0
”
), the
logic level at the
EA
pin is sampled and latched during
RST deassertion. Subsequent changes in logic levels
on
EA
have no effect. If the device is powered-up with-
out a reset (RST), the latch initializes to a random value
and holds that value until RST is pulsed high, then low.
It is necessary that the latched value of
EA
be in agree-
ment with the current logic level at that pin in order for
the device to function properly.
Signature Bytes
The MAX7651/MAX7652 contain three signature bytes
with the information shown in Table 23. Read each byte
by following the
Flash Memory Read
procedure, but set
P2.6, P2.7, P3.6, and P3.7 at low. Signature bytes are
not affected by mass erase or page erase operations.
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
EEDAT7
EEDAT6
EEDAT5
EEDAT4
EEDAT3
EEDAT2
EEDAT1
EEDAT0
Table 21. Flash Memory Data (EEDAT) Format
—
SFR Address ECH
BIT 7
(MSB)
RDYHI/
EECMD7
BIT 6
RDYLO/
EECMD6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
EECMD5
EECMD4
EECMD3
EECMD2
EECMD1
EECMD0
BIT
NAME
DESCRIPTION
7
RDYHI
High Block Ready Status. The MAX7651/MAX7652 set RDYHI to 0 during read, write, and page-
erase operations that are applied to the 8-kbyte
“
high
”
block of flash memory. The bit is
otherwise set to 1.
6
RDYLO
Low Block Ready Status. The MAX7651/MAX7652 set RDYLO to 0 during read, write, and page-
erase operations that are applied to the 8-kbyte
“
low
”
block of flash memory. The bit is otherwise
set to 1.
7 - 0
EECMD
Flash Memory Command Bits. Used to specify read, write, or page-erase memory commands.
EECMD7 is the MSB.
Table 22. Flash Status and Control (EESTCMD) Format
—
SFR Address EDH
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