![](http://datasheet.mmic.net.cn/370000/MAX7456_datasheet_16716529/MAX7456_9.png)
M
Single-Channel Monochrome On-Screen
Display with Integrated EEPROM
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9
Pin Description
PIN
NAME
FUNCTION
1, 2, 13–16,
27, 28
N.C.
No Connection. Not internally connected.
3
4
DGND
Digital Power-Supply Input. Bypass to DGND with a 0.1μF capacitor.
Digital Ground
5
CLKIN
Crystal Connection 1. Connect a parallel resonant, fundamental mode crystal between CLKIN and XFB
for use as a crystal oscillator, or drive CLKIN directly with a 27MHz system reference clock.
6
XFB
Crystal Connection 2. Connect a parallel resonant, fundamental mode crystal between CLKIN and XFB
for use as a crystal oscillator, or leave XFB unconnected when driving CLKIN with a 27MHz system
reference clock.
7
8
9
10
11
CLKOUT
CS
SDIN
SCLK
SDOUT
Clock Output. 27MHz logic-level output system clock.
Active-Low Chip-Select Input. SDOUT goes high impedance when
CS
is high.
Serial Data Input. Data is clocked in at rising edge of SCLK.
Serial Clock Input. Clocks data into SDIN and out of SDOUT. Duty cycle must be between 40% and 60%.
Serial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when
CS
is high.
12
LOS
Loss-of-Sync Output (Open-Drain). LOS goes high when the VIN sync pulse is lost for 32 consecutive
lines. LOS goes low when 32 consecutive valid sync pulses are received. Connect to a 1k
pullup
resistor to DVDD or another positive supply voltage suitable for the receiving device.
17
VSYNC
Vertical Sync Output (Open-Drain).
VSYNC
goes low following the video input’s vertical sync interval.
VSYNC
is either recovered from VIN or internally generated when in internal sync mode. Connect to a
1k
pullup resistor to DVDD or another positive supply voltage suitable for the receiving device.
18
HSYNC
Horizontal Sync Output (Open-Drain).
HSYNC
goes low following the video input’s horizontal sync
interval.
HSYNC
is either recovered from VIN or internally generated when in internal sync mode. Connect
to a 1k
pullup resistor to DVDD or another positive supply voltage suitable for the receiving device.
19
RESET
System Reset Input. The minimum
RESET
pulse width is 50ms. All SPI registers are reset to their default
values after 100μs following the rising edge of
RESET
. These registers are not accessible for reading or
writing during that time. The display memory is reset to its default value of 00H in all locations after 20μs
following the rising edge of
RESET
.
20
21
22
23
24
25
26
AGND
AVDD
VIN
PGND
PVDD
SAG
VOUT
Analog Ground
Analog Power-Supply Input. Bypass to AGND with a 0.1μF capacitor.
PAL or NTSC CVBS Video Input
Driver Ground. Connect to AGND at a single point.
Driver Power-Supply Input. Bypass to PGND with a 0.1μF capacitor.
Sag Correction Input. Connect to VOUT if not used. See Figure 1b.
Video Output
—
EP
Exposed Pad. Internally connected to AGND. Connect EP to the AGND plane for improved heat
dissipation. Do not use EP as the only ground connection.