參數(shù)資料
型號(hào): MAX7456
廠商: Maxim Integrated Products, Inc.
英文描述: Single-Channel Monochrome On-Screen Display with Integrated EEPROM
中文描述: 集成了EEPROM的單通道、單色隨屏顯示器
文件頁(yè)數(shù): 10/43頁(yè)
文件大小: 604K
代理商: MAX7456
M
Single-Channel Monochrome On-Screen
Display with Integrated EEPROM
10
______________________________________________________________________________________
Detailed Description
The MAX7456 single-channel monochrome on-screen
display (OSD) generator integrates all the functions need-
ed to generate a user-defined OSD and insert it into the
output signal. The MAX7456 accepts a composite NTSC
or PAL video signal. The device includes an input clamp,
sync separator, video timing generator, OSD insertion
mux, nonvolatile character memory, display memory,
OSD generator, crystal oscillator, an SPI-compatible inter-
face to read/write the OSD data, and a video driver (see
the
Simplified Functional Diagram
). Additionally, the
MAX7456 provides vertical sync (
VSYNC
), horizontal
sync (
HSYNC
), and loss-of sync (LOS) outputs for system
synchronization. A clock output signal (CLKOUT) allows
daisy-chaining of multiple devices.
See the
MAX7456 Register Description
section for an
explanation of register notation use in this data sheet.
The 256 user-defined 12 x 18 pixel character set
comes preloaded and is combined with the input video
stream to generate a CVBS signal with OSD video out-
put. A maximum of 256 12 x 18 pixel characters can be
reprogrammed in the NVM. In NTSC mode, 13 rows x
30 characters are displayed. In PAL mode, 16 rows x
30 characters are displayed. When the input video sig-
nal is absent, the OSD image can still be displayed by
using the MAX7456’s internal video timing generator.
Video Input
The MAX7456 accepts standard NTSC or PAL CVBS
signals at VIN. The video signal input must be AC-cou-
pled with a 0.1μF capacitor and is internally clamped.
An input coupling capacitance of 0.1μF is required to
guarantee the specified line-time distortion (LTD) and
video clamp settling time. The video clamp settling time
changes proportionally to the input coupling capaci-
tance, and LTD changes inversely proportional to the
capacitance.
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MAX7456
N.C.
SDIN
+5V
27MHz
SDOUT
+5V
CVBS OUT
SAG
PGND
RESET
HSYNC
VSYNC
DGND
CLKIN
XFB
CLKOUT
CS
SDIN
SCLK
SDOUT
LOS
N.C.
SCLK
CS
CVBS IN
LOS
VS
HS
N.C.
N.C.
N.C.
CLKOUT
N.C.
AGND
N.C.
N.C.
+5V
0.1
μ
F
C
OUT
75
75
1k
1k
1k
0.1
μ
F
0.1
μ
F
0.1
μ
F
C
SAG
DVDD
VOUT
PVDD
VIN
AVDD
Figure 2. Typical Operating Circuit
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