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參數(shù)資料
| 型號(hào)： | MAX7360EWX+T |
| 廠(chǎng)商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 7/32頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CTRLR KEY-SWITCH I2C 36-WLP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類(lèi)型： | 控制器 |
| 輸入類(lèi)型： | 邏輯 |
| 輸出類(lèi)型： | 邏輯 |
| 接口： | I²C，2 線(xiàn)串口 |
| 電流 - 電源： | 50µA |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 36-WFBGA，WLCSP |
| 供應(yīng)商設(shè)備封裝： | 36-WLP（2.57x2.57） |
| 包裝： | 帶卷 (TR) |
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15
Maxim Integrated
I2C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
MAX7360
Figure 5. Acknowledge
Figure 6. Slave Address
Slave Addresses
The MAX7360 has a 7-bit long slave address (Figure
6). The bit following a 7-bit slave address is the R/W bit,
which is low for a write command and high for a read
command.
The first 4 bits (MSBs) of the MAX7360 slave address
are always 0111. Slave address bits A3, A2, and A1
correspond, by the matrix in Table 3, to the states of the
device address input AD0, and A0 corresponds to the
R/W bit. The AD0 input can be connected to any of four
signals (GND, VCC, SDA, or SCL), giving four possible
slave address pairs and allowing up to four MAX7360
devices to share the bus. Because SDA and SCL are
dynamic signals, care must be taken to ensure that AD0
transitions no sooner than the signals on SDA and SCL.
The MAX7360 monitors the bus continuously, waiting for a
START condition, followed by its slave address. When the
MAX7360 recognizes its slave address, it acknowledges
and is then ready for continued communication.
Bus Timeout
The MAX7360 features a 20ms minimum bus timeout
on the 2-wire serial interface, largely to prevent the
MAX7360 from holding the SDA I/O low during a read
transaction should the SCL lock up for any reason before
a serial transaction is completed. Bus timeout operates
by causing the MAX7360 to internally terminate a serial
Figure 7. Command Byte Received
Figure 8. Command and Single Data Byte Received
SCL
SDA
BY
TRANSMITTER
CLOCK PULSE FOR
ACKNOWLEDGE
START
CONDITION
SDA
BY
RECEIVER
1
2
8
9
S
SDA
SCL
0
1
A3
A2
A1
1
MSB
LSB
ACK
R/W
S
A
P
0
SLAVE ADDRESS
COMMAND BYTE
D7
D6
D5
D4
D3
D2
D1
D0
COMMAND BYTE IS STORED ON RECEIPT OF
ACKNOWLEDGE CONDITION
ACKNOWLEDGE FROM MAX7360
R/W
S
A
P
0
SLAVE ADDRESS
COMMAND BYTE
DATA BYTE
1 BYTE
AUTOINCREMENT
COMMAND BYTE ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
D1
D0
D3
D2
D5
D4
D7
D6
ACKNOWLEDGE FROM MAX7360
R/W
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