參數(shù)資料
型號(hào)： MAX7360EWX+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 6/32頁(yè)
文件大小： 0K
描述： IC CTRLR KEY-SWITCH I2C 36-WLP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
類型： 控制器
輸入類型： 邏輯
輸出類型： 邏輯
接口： I²C，2 線串口
電流 - 電源： 50µA
安裝類型： 表面貼裝
封裝/外殼： 36-WFBGA，WLCSP
供應(yīng)商設(shè)備封裝： 36-WLP（2.57x2.57）
包裝： 帶卷 (TR)
14
Maxim Integrated
I2C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
MAX7360
is required on SDA. The MAX7360’s SCL line operates
only as an input. A pullup resistor is required on SCL if
there are multiple masters on the 2-wire interface, or if
the master in a single-master system has an open-drain
SCL output.
Each transmission consists of a START (S) condition
(Figure 3) sent by a master, followed by the MAX7360
7-bit slave address plus R/W bit, a register address byte,
one or more data bytes, and finally, a STOP (P) condition.
START and STOP Conditions
Both SCL and SDA remain high when the interface is not
busy. A master signals the beginning of a transmission
with a START condition by transitioning SDA from high
to low while SCL is high. When the master has finished
communicating with the slave, it issues a STOP condition
by transitioning SDA from low to high while SCL is high.
The bus is then free for another transmission.
Bit Transfer
One data bit is transferred during each clock pulse
(Figure 4). The data on SDA must remain stable while
SCL is high.
Acknowledge
The acknowledge bit is a clocked 9th bit (Figure 5), which
the recipient uses to handshake receipt of each byte of
data. Thus, each byte transferred effectively requires
9 bits. The master generates the 9th clock pulse, and
the recipient pulls down SDA during the acknowledge
clock pulse; therefore, the SDA line is stable low during
the high period of the clock pulse. When the master is
transmitting to the MAX7360, the MAX7360 generates
the acknowledge bit because the MAX7360 is the recipi-
ent. When the MAX7360 is transmitting to the master,
the master generates the acknowledge bit because the
master is the recipient.
Figure 3. START and STOP Conditions
Figure 4. Bit Transfer
Table 3. 2-Wire Interface Address Map
PIN AD0
DEVICE ADDRESS
A7
A6
A5
A4
A3
A2
A1
A0
GND
0
1
0
R/W
VCC
0
1
0
1
0
R/W
SDA
0
1
0
R/W
SCL
0
1
0
R/W
SDA
SCL
START
CONDITION
STOP
CONDITION
S
P
SDA
SCL
DATA LINE STABLE;
DATA VALID
CHANGE OF DATA
ALLOWED
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