參數(shù)資料
型號(hào): MAX5866ETM+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 5/26頁(yè)
文件大?。?/td> 0K
描述: IC ANLG FRONT END 60MSPS 48-TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 43
位數(shù): 10
通道數(shù): 4
功率(瓦特): 2.10W
電壓 - 電源,模擬: 2.7 V ~ 3.3 V
電壓 - 電源,數(shù)字: 2.7 V ~ 3.3 V
封裝/外殼: 48-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-TQFN-EP(7x7)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 1398 (CN2011-ZH PDF)
Detailed Description
The MAX5866 integrates dual 8-bit receive ADCs and
dual 10-bit transmit DACs while providing ultra-low
power and highest dynamic performance at a conver-
sion rate of 60Msps. The ADCs’ analog input amplifiers
are fully differential and accept 1VP-P full-scale signals.
The DACs’ analog outputs are fully differential with
±400mV full-scale output range at 1.4V common mode.
The MAX5866 includes a 3-wire serial interface to con-
trol operating modes and power management. The ser-
ial interface is SPI and MICROWIRE compatible.
The MAX5866 serial interface selects shutdown, idle,
standby, transmit, receive, and transceiver modes.
The MAX5866 can operate in FDD or TDD applications
by configuring the device for transmit, receive, or trans-
ceiver modes through a 3-wire serial interface. In TDD
mode, the digital bus for receive ADC and transmit
DAC can be shared to reduce the digital I/O to a single
10-bit parallel multiplexed bus. In FDD mode, the
MAX5866 digital I/O can be configured for an 18-bit,
parallel multiplexed bus to match the dual 8-bit ADC
and dual 10-bit DAC.
The MAX5866 features an internal precision 1.024V
bandgap reference that is stable over the entire power-
supply and temperature ranges.
MAX5866
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
______________________________________________________________________________________
13
SPI is a trademark of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
Figure 1. MAX5866 ADC Internal T/H Circuits
S3b
S3a
COM
S5b
S5a
QA+
QA-
S1
OUT
C2a
C2b
S4c
S4a
S4b
C1b
C1a
INTERNAL
BIAS
INTERNAL
BIAS
COM
HOLD
CLK
INTERNAL
NONOVERLAPPING
CLOCK SIGNALS
TRACK
S2a
S2b
S3b
S3a
COM
S5b
S5a
IA+
IA-
S1
OUT
C2a
C2b
S4c
S4a
S4b
C1b
C1a
INTERNAL
BIAS
INTERNAL
BIAS
COM
S2a
S2b
MAX5866
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