- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄2011 > MAX5866ETM+ (Maxim Integrated Products)IC ANLG FRONT END 60MSPS 48-TQFN PDF資料下載
參數(shù)資料
| 型號： | MAX5866ETM+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 10/26頁 |
| 文件大小： | 0K |
| 描述： | IC ANLG FRONT END 60MSPS 48-TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 43 |
| 位數(shù)： | 10 |
| 通道數(shù)： | 4 |
| 功率（瓦特）： | 2.10W |
| 電壓 - 電源，模擬： | 2.7 V ~ 3.3 V |
| 電壓 - 電源，數(shù)字： | 2.7 V ~ 3.3 V |
| 封裝/外殼： | 48-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-TQFN-EP（7x7） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1398 (CN2011-ZH PDF) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當(dāng)前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁
MAX5866
Mode Recovery Timing
Figure 6 shows the mode recovery timing diagram.
tWAKE is the wake-up time when exiting shutdown, idle,
or standby mode and entering into Rx, Tx, or Xcvr
mode. tENABLE is the recovery time when switching
between any Rx, Tx, or Xcvr mode. tWAKE or tENABLE is
the time for the ADC to settle within 1dB of specified
SINAD performance and DAC settling to 10 LSB error.
tWAKE or tENABLE times are measured after the 8-bit
serial command is latched into the MAX5866 by CS
transitioning high. tENABLE for Xcvr mode is dominated
by the DAC wake-up time. The recovery time is 10s to
switch between Xcvr, Tx, or Rx modes. The recovery
time is 40s to switch from shutdown or standby mode
to Xcvr mode.
System Clock Input (CLK)
CLK input is shared by both the ADCs and DACs. It
accepts a CMOS-compatible signal level set by OVDD
from +2.7V to VDD. Since the interstage conversion of
the device depends on the repeatability of the rising
and falling edges of the external clock, use a clock with
low jitter and fast rise and fall times (<2ns). Specifically,
sampling occurs on the rising edge of the clock signal,
requiring this edge to provide the lowest possible jitter.
Any significant clock jitter limits the SNR performance
of the on-chip ADCs as follows:
where fIN represents the analog input frequency and
tAJ is the time of the clock jitter.
SNR
tt
IN
AJ
=×
××
×
20
1
2
log
π
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
18
______________________________________________________________________________________
Figure 5. 3-Wire Serial Interface Timing Diagram
MSB
CS
SCLK
DIN
LSB
tCSW
tCS
tCP
tCSS
tCL
tCH
tDS
tDH
Figure 6. MAX5866 Mode Recovery Timing Diagram
CS
SCLK
DIN
ID/QD
DAO–DA7
8-BIT DATA
ADC DIGITAL OUTPUT.
SINAD SETTLES WITHIN 1dB
DAC ANALOG OUTPUT. OUTPUT
SETTLES TO 10 LSB ERROR
tWAKE, SD, ST_ (Rx) OR tENABLE, Rx
tWAKE, SD, ST_ (Tx) OR tENABLE TX
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX5873EGK+D | IC DAC 12BIT 200MSPS DUAL 68-QFN |
| MAX5874EGK+D | IC DAC 14BIT 200MSPS DUAL 68-QFN |
| MAX5875EGK+D | IC DAC 16BIT DUAL 200MSPS 68-QFN |
| MAX5876EGK+D | IC DAC 12BIT DUAL 250MSPS 68-QFN |
| MAX5877EGK+D | IC DAC 14BIT DUAL 250MSPS 68-QFN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX5866ETM+ | 功能描述:ADC / DAC多通道 10-Bit 2Ch 60Msps CODEC/AFE RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40 |
| MAX5866ETM+T | 功能描述:ADC / DAC多通道 10-Bit 2Ch 60Msps CODEC/AFE RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40 |
| MAX5866ETM-T | 功能描述:ADC / DAC多通道 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40 |
| MAX5868EXE+ | 制造商:Maxim Integrated Products 功能描述:- Rail/Tube |
| MAX5873EGK | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。