Figure 3 shows the relationship between the clock, ana- log inputs, and " />
參數(shù)資料
型號(hào)： MAX5865ETM+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 7/26頁(yè)
文件大?。?/td> 0K
描述： IC ANLG FRONT END 40MSPS 48-TQFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 10
通道數(shù)： 4
功率（瓦特）： 2.10W
電壓 - 電源，模擬： 2.7 V ~ 3.3 V
電壓 - 電源，數(shù)字： 1.8 V ~ 3.3 V
封裝/外殼： 48-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 48-TQFN-EP（7x7）
包裝： 帶卷 (TR)
ADC System Timing Requirements
Figure 3 shows the relationship between the clock, ana-
log inputs, and the resulting output data. Channel IA
(CHI) and channel QA (CHQ) are simultaneously sam-
pled on the rising edge of the clock signal (CLK) and
the resulting data is multiplexed at the DA0–DA7 out-
puts. CHI data is updated on the rising edge and CHQ
data is updated on the falling edge of the CLK.
Including the delay through the output latch, the total
clock-cycle latency is 5 clock cycles for CHI and 5.5
clock cycles for CHQ.
Dual 10-Bit DAC
The 10-bit DACs are capable of operating with clock
speeds up to 40MHz. The DAC’s digital inputs,
DD0–DD9, are multiplexed on a single 10-bit bus. The
voltage reference determines the data converters’ full-
scale output voltages. See the Reference Configurations
section for setting reference voltage. The DACs utilize a
current-array technique with a 1mA (with 1.024V refer-
ence) full-scale output current driving a 400
internal
resistor resulting in a
±400mV full-scale differential out-
put voltage. The MAX5865 is designed for differential
output only and is not intended for single-ended appli-
cation. The analog outputs are biased at 1.4V common
mode and designed to drive a differential input stage
with input impedance
≥70k. This simplifies the analog
interface between RF quadrature upconverters and the
MAX5865. RF upconverters require a 1.3V to 1.5V com-
mon-mode bias. The internal DC common-mode bias
eliminates discrete level setting resistors and code-gen-
erated level-shifting while preserving the full dynamic
range of each transmit DAC. Table 2 shows the output
voltage vs. input code.
MAX5865
Ultra-Low-Power, High-Dynamic-
Performance, 40Msps Analog Front End
______________________________________________________________________________________
15
Figure 2. ADC Transfer Function
INPUT VOLTAGE (LSB)
-1
-126 -125
256
2 x VREF
1 LSB =
VREF = VREFP - VREFN
VREF
V
REF
V
REF
0+1
-127
+126
+128
+127
-128
+125
(COM)
OFFSET
BINAR
Y
OUTPUT
CODE
(LSB)
0000 0000
0000 0001
0000 0010
0000 0011
1111 1111
1111 1110
1111 1101
0111 1111
1000 0000
1000 0001
Figure 3. ADC System Timing Diagram
tDOQ
tDOI
5 CLOCK-CYCLE LATENCY (CHI), 5.5 CLOCK-CYCLE LATENCY (CHQ)
DA0–DA7
D0Q
D1I
D1Q
D2I
D2Q
D3I
D3Q
D4I
D4Q
D5I
D5Q
D6I
D6Q
CHI
CHQ
CLK
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MAX5865EVKIT 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開(kāi)發(fā)工具 Evaluation Kit for the MAX5863 MAX5864 MAX5865 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類(lèi)型:ADC 工具用于評(píng)估:ADS130E08 接口類(lèi)型:SPI 工作電源電壓:- 6 V to + 6 V
MAX5866ETM 功能描述:ADC / DAC多通道 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類(lèi)型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX5866ETM+ 功能描述:ADC / DAC多通道 10-Bit 2Ch 60Msps CODEC/AFE RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類(lèi)型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX5866ETM+T 功能描述:ADC / DAC多通道 10-Bit 2Ch 60Msps CODEC/AFE RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類(lèi)型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX5866ETM-T 功能描述:ADC / DAC多通道 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類(lèi)型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
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