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參數資料
| 型號： | MAX5312EAE+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 6/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT 5V/10V SER 16-SSOP |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,000 |
| 設置時間： | 10µs |
| 位數： | 12 |
| 數據接口： | 串行 |
| 轉換器數目： | 1 |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 16-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | * |
MAX5312
Data in the shift register is transferred to the input register
during the appropriate software command only. Data in
the input register is transferred to the DAC register in one
of two ways: using the software command, or through
external logic control using the asynchronous load input
(LDAC). Table 2 shows the software commands that
transfer the data from the shift register to the input and/or
DAC registers. The CLR, an external logic control, asyn-
chronously forces the input and DAC registers to zero
code, and the output to 0V, in both unipolar and bipolar
modes. The interface timing is shown in Figures 2 and 3.
Wait a minimum of 100ns after CS goes high before
implementing LDAC or CLR. If either of these logic
inputs activates during a data transfer, the incoming
data is corrupted and needs to be reloaded. For soft-
ware control only, connect LDAC and CLR high.
DAC Architecture
The MAX5312 uses an inverted DAC ladder architec-
ture to convert the digital input into an analog output
voltage. The digital input controls weighted-switches
that connect the DAC ladder nodes to either REF or
GND (Figure 4). The sum of the weights produces the
analog equivalent of the digital-input word and is then
buffered at the output.
±10V, 12-Bit, Serial, Voltage-Output DAC
14
______________________________________________________________________________________
CONTROL BITS
DATA BITS
MSB
LSB
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Table 1. Serial-Data Format
CONTROL BITS*
INPUT DATA
C3
C2
C1
C0
D11–D0
FUNCTION
0
XXXXXXXXXXXX
No operation; command is ignored.
0
1
0
12-bit DAC data
Load input register from shift register; DAC output unchanged.
0
1
0
12-bit DAC data
Load input and DAC registers from shift register; DAC output updated.
0
1
0
XXXXXXXXXXXX
Load DAC register from input register; DAC output updated; input register unchanged.
1
0
XXXXXXXXXXXX
Enter shutdown; input and DAC registers unchanged.
1
0
XXXXXXXXXXXX
Exit shutdown; input and DAC registers unchanged.
Table 2. Serial-Interface Programming Commands
X = Don’t care.
*All unlisted commands are reserved commands. Do not use.
SCLK
DIN
COMMAND EXECUTED
9
8
16
(1)
1
C2
C3
D0
C1
C0
D11
D10
D9
D6
D5
D4
D3
D2
D1
D8
D7
CS
Figure 2. Serial-Interface Signals
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