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參數(shù)資料
| 型號： | MAX5312EAE+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 4/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT 5V/10V SER 16-SSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 設(shè)置時(shí)間： | 10µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | * |
MAX5312
±10V, 12-Bit, Serial, Voltage-Output DAC
12
______________________________________________________________________________________
PIN
NAME
FUNCTION
1
SCLK
Serial-Clock Input. Data is shifted from DIN into the internal register on the rising edge of SCLK. Data is
clocked out at DOUT on the falling edge of SCLK. SCLK is active only while CS is low.
2
DIN
Serial-Data Input. DIN is the data input port for the serial interface. Clock data in on the rising edge of SCLK.
3
CS
Active-Low Chip-Select Input. CS activates the serial interface. Drive CS low to initiate serial communication.
4DOUT
Serial-Data Output. DOUT is the data output port for the serial interface. Data shifted into DIN appears at
DOUT 16.5 clock cycles later, valid on the falling edge of SCLK. DOUT is high impedance when CS is high.
5
DGND
Digital Ground
6VCC
Digital Power Input. VCC ranges from +2.7V to +5.5V. Bypass VCC with a 0.1F and 1.0F capacitor to
7
SHDN
Active-Low Shutdown Input. SHDN places the device into low-power shutdown mode. When shut down
REF and DOUT are high impedance, drive SHDN low to place the device into shutdown mode.
8
UNI/BIP
Unipolar/Bipolar-Select Input. UNI/BIP selects unipolar or bipolar output. In unipolar mode, the analog
output range is 0 to (+2 x VREF). In bipolar mode, the analog output range is (-2 x VREF) to (+2 x VREF).
Drive UNI/BIP high for unipolar output. Drive UNI/BIP low for bipolar output. Dual supplies are required for
bipolar operation.
9
OUT
Analog Output. OUT is the output port for the DAC. Read OUT relative to SGND.
10
SGND
Signal Ground. SGND is the ground-reference node for the output amplifier’s internal feedback resistors.
Connect SGND directly to AGND. (See Figure 1.)
11
AGND
Analog Ground. AGND is the ground return for VDD and VSS.
12
VSS
Negative Power Input. Bypass VSS with a 0.1F and 1.0F capacitor to AGND. If operating with a single
supply, connect VSS to AGND.
13
REF
External Reference Input. Apply an external reference voltage of +2V to +5.25V to REF to determine the
output voltage range. In unipolar mode, the output range is from 0 to (+2 x VREF). In bipolar mode, the
output range is from (-2 x VREF) to (+2 x VREF).
14
VDD
Positive Power Input. Bypass VDD with a 0.1F and 1.0F capacitor to AGND.
15
CLR
Active-Low Clear Input. CLR clears input and DAC registers and resets the DAC output to 0V. Drive CLR
low to assert the clear condition.
16
LDAC
Active-Low Load Input. Use LDAC to update the DAC register. LDAC is an asynchronous control input.
Drive low to force an update.
Pin Description
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