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參數(shù)資料
| 型號： | MAX5312EAE+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 16/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT 5V/10V SER 16-SSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 設(shè)置時間： | 10µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | * |
MAX5312
±10V, 12-Bit, Serial, Voltage-Output DAC
6
_______________________________________________________________________________________
TIMING CHARACTERISTICS
(VDD = +15V, VSS = -15V or 0V, VCC = +2.7V to +5.5V, AGND = DGND = SGND = 0, VREF = 5V, RLOAD = 2k
Ω, CLOAD = 250pF, TA
= TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25
°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Frequency
10
MHz
SCLK Clock Period
tCP
100
ns
SCLK Pulse-Width High
tCH
For nondaisy-chain use
45
ns
SCLK Pulse-Width Low
tCL
For nondaisy-chain use
45
ns
CS Fall to SCLK Rise Setup Time
tCSS
40
ns
+2.7V
≤ VCC ≤ +3.6V
15
SCLK Rise to CS Rise Hold Time
tCSH
+4.5V
≤ VCC ≤ +5.5V
10
ns
DIN Setup Time
tDS
20
ns
DIN Hold Time
tDH
10
ns
LDAC Pulse Width
tLD
50
ns
+2.7V
≤ VCC ≤ +3.6V
100
CS Rise to LDAC Low Setup Time
tLDS
+4.5V
≤ VCC ≤ +5.5V
50
ns
CLOAD = 20pF, +2.7V
≤ VCC ≤ +3.6V
100
SCLK Fall to DOUT Valid
Propagation Delay
tDO1
CLOAD = 20pF, +4.5V
≤ VCC ≤ +5.5V
80
ns
SCLK Rise to CS Fall Delay
tCS0
10
ns
CS Low to DOUT Valid Time
tCSE
CLOAD = 20pF
120
ns
CS High to DOUT Disabled Time
tCSD
120
ns
CS Rise to SCLK Rise Hold Time
tCS1
50
ns
+2.7V
≤ VCC ≤ +3.6V
200
CS Pulse-Width High
tCSW
+4.5V
≤ VCC ≤ +5.5V
100
ns
CLR Pulse-Width Low
tCLR
50
ns
Note 1: Output unloaded, digital inputs = VCC or DGND.
Note 2:
ΔVDD = +14.5V to +15.5V, ΔVSS = -15.5V to -14.5V, code = FFF.
Note 3: Measured from code 14hex to FFFhex.
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