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參數(shù)資料
| 型號(hào)： | MAX3981UTH+T |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 7/9頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC XAUI QUAD EQUAL 44-TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 44-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 44-TQFN-EP（7x7） |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
tion of the signal detect (SDET) function. For constant
operation, connect the EN signal directly to VCC.
Signal Detect with Standby Mode
Signal activity is detected on channel 1 only (IN1±).
When the peak-to-peak differential voltage at IN1± is
less than 30mVp-p, the TTL output SDET goes low.
When the peak-to-peak differential voltage becomes
greater than 100mVp-p, SDET is asserted high. SDET
can be used to automatically force the equalizer into
standby mode by connecting SDET directly to the EN
input. When not used, SDET should not be connected.
The signal-detect function continues to operate while
the part is in standby mode. While connected to the EN
pin, the signal detect can “wake up” the part and
resume normal operation.
Layout Considerations
Circuit board layout and design can significantly affect
the MAX3981 performance. Use good high-frequency
design techniques, including minimizing ground induc-
tances and vias and using controlled-impedance trans-
mission lines for the high-frequency data signals.
Signals should be routed differentially to reduce EMI
susceptibility and crosstalk. Power-supply decoupling
capacitors should be placed as close as possible to
the VCC pins.
MAX3981
3.125Gbps XAUI Quad Cable Equalizer
_______________________________________________________________________________________
7
VCC
1.2k
Ω
50
Ω
50
Ω
200
μA
IN+
IN-
ESD
STRUCTURES
Figure 2. CML Input Buffer
50
Ω
50
Ω
VCC
Q1
Q2
OUT+
OUT-
DATA
ESD
STRUCTURES
Figure 3. CML Output Buffer
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