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參數(shù)資料
| 型號(hào)： | MAX3981UTH+T |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 6/9頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC XAUI QUAD EQUAL 44-TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 44-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 44-TQFN-EP（7x7） |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
MAX3981
Detailed Description
Receiver and Transmitter
The adaptive equalizer accepts four lanes of
3.125Gbps CML digital data signals and compensates
each received signal for dielectric and skin losses. A
limiting amp shapes the output of the equalizer and the
output driver transmits the regenerated XAUI lanes as
CML signals. The source impedance and termination
impedance are 100
Ω differential.
General Theory of Operation
Internally, the MAX3981 is comprised of signal-detect
circuitry, four matched equalizers, and one equalizer
control loop. The four equalizers are made up of a mas-
ter equalizer and three slave equalizers. The adaptive
control is generated from only channel 1. It is assumed
that all channels have the same characterization in fre-
quency content, coding, and transmission length.
The master equalizer consists of the following func-
tions: signal detect, adaptive equalizer, equalizer con-
trol, limiting and output drivers. The signal detect
indicates input signal power. When the input signal
level is sufficiently high, the SDET output is asserted.
This does not directly control the operation of the part.
The equalizer core reduces intersymbol interference
(ISI), compensating for frequency-dependent, media-
induced loss. The equalization control detects the
spectral contents of the input signal and provides a
control voltage to the equalizer core, adapting it to dif-
ferent media. The equalizer operation is optimized for
short-run DC-balanced transmission codes such as
8b/10b codes.
CML Input and Output Buffers
The input and output buffers are implemented using
current-mode logic (CML). Equivalent circuits are shown
in Figures 2 and 3. For details on interfacing with CML,
see Maxim application note HFAN-1.0,
Interfacing
Between CML, PECL, and LVDS. The common-mode
voltages of the input and output are above 2.5V. AC-
coupling capacitors are required when interfacing this
part. Values of 0.10F or greater are recommended.
Media Equalization
Equalization at the input port compensates for the high-
frequency loss encountered with twin-axial cable or
shielded twisted pair. This part is optimized for 10ft
(3m) and 3.125Gbps; however, the part will reduce ISI
for signals spanning longer distances and functions for
data rates from 2Gbps to 4Gbps providing that short-
length balanced codes, such as 8b/10b, are used.
Applications Information
Standby Mode
The standby state allows reduced-power operation.
The TTL input, EN, must be set to TTL high for normal
operation. A TTL low at EN forces the equalizer into the
standby state. The signal EN does not affect the opera-
3.125Gbps XAUI Quad Cable Equalizer
6
_______________________________________________________________________________________
IN1+
IN1-
EQUALIZER
LIMITING
AMP
2
3
4
2
3
4
2
3
4
2
3
4
2
3
4
2
3
4
OUT1+
OUT1-
2
3
4
2
3
4
EN
POWER
MANAGEMENT
SDET FUNCTION IS
INDEPENDENT OF EN
SDET
TTL
CML
SIGNAL
DETECT
IP1, IN1 ONLY
MAX3981
Functional Diagram
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