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參數(shù)資料
| 型號： | MAX3890ECB+TD |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 8/12頁 |
| 文件大小： | 0K |
| 描述： | IC 16:1 SERIALIZER 64-TQFP-EP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 功能： | 串行器 |
| 數(shù)據(jù)速率： | 2.5Gbps |
| 輸入類型： | LVDS |
| 輸出類型： | PECL |
| 輸入數(shù)： | 16 |
| 輸出數(shù)： | 1 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-TQFP-EP（10x10） |
| 包裝： | 帶卷 (TR) |
MAX3890
+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer
with Clock Synthesis and LVDS Inputs
_______________________________________________________________________________________
5
Pin Description
NAME
FUNCTION
1, 17, 33, 48, 49, 63
GND
Ground
2, 5, 7, 10, 13,
14, 32, 56, 60, 64
VCC
+3.3V Supply Voltage
PIN
3
SLBO-
System Loopback Inverting Output. Enabled when SOS is high.
4
SLBO+
System Loopback Noninverting Output. Enabled when SOS is high.
12
SDO+
Noninverting PECL Serial-Data Output
9
SCLKO+
Noninverting PECL Serial Clock Output
6
SOS
System Loopback Output Select. System loopback disabled when low.
55
PCLKO-
Inverting LVDS Parallel Clock Output. Use positive transition of PCLKO to clock the over-
head management circuit.
54
PCLKO+
Noninverting LVDS Parallel Clock Output. Use positive transition of PCLKO to clock the
overhead management circuit.
57
RCLK+
Noninverting LVDS Reference Clock Input. Connect an LVDS-compatible crystal refer-
ence clock to the RCLK inputs.
59
CLKSET
Reference Clock Rate Programming Pin:
CLKSET = VCC: Reference Clock Rate = 155.52MHz
CLKSET = Open: Reference Clock Rate = 77.76MHz
CLKSET = 20k
to GND: Reference Clock Rate = 51.84MHz
CLKSET = GND: Reference Clock Rate = 38.88MHz
58
RCLK-
Inverting LVDS Reference Clock Input. Connect an LVDS-compatible crystal reference
clock to the RCLK inputs.
61
FIL-
Filter Capacitor Input. Connect a 330nF capacitor between FIL+ and FIL-.
18, 20, 22, 24, 26,
28, 30, 34, 36, 38,
40, 42, 44, 46, 50, 52
PDI15+ to
PDI0+
Noninverting LVDS Parallel Data Inputs. Data is clocked on the PCLKI positive transition.
62
FIL+
Filter Capacitor Input. Connect a 330nF capacitor between FIL+ and FIL-.
8
SCLKO-
Inverting PECL Serial Clock Output
11
SDO-
Inverting PECL Serial-Data Output
15
PCLKI+
Noninverting LVDS Parallel Clock Input. Connect the incoming parallel-clock signal to the
PCLKI inputs. Note that data is updated on the positive transition of the PCLKI signal.
16
PCLKI-
Inverting LVDS Parallel Clock Input. Connect the incoming parallel-clock signal to the PCLKI
inputs. Note that data is updated on the positive transition of the PCLKI signal.
19, 21, 23, 25, 27,
29, 31, 35, 37, 39,
41, 43, 45, 47, 51, 53
PDI15- to
PDI0-
Inverting LVDS Parallel Data Inputs. Data is clocked on the PCLKI positive transition.
EP
Exposed
Pad
Ground. This must be soldered to a circuit board for proper thermal performance (see
Package Information).
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