參數(shù)資料
型號: MAX3890ECB+TD
廠商: Maxim Integrated Products
文件頁數(shù): 11/12頁
文件大小: 0K
描述: IC 16:1 SERIALIZER 64-TQFP-EP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 750
功能: 串行器
數(shù)據(jù)速率: 2.5Gbps
輸入類型: LVDS
輸出類型: PECL
輸入數(shù): 16
輸出數(shù): 1
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-TQFP-EP(10x10)
包裝: 帶卷 (TR)
MAX3890
+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer
with Clock Synthesis and LVDS Inputs
8
_______________________________________________________________________________________
MAX3890
SCLKO+
OR SDO+
SCLKO-
OR SDO-
VCC - 2V
50
50
Z0 = 50
HIGH-
IMPEDANCE
INPUTS
Z0 = 50
MAX3890
SCLKO+
OR SDO+
SCLKO-
OR SDO-
+3.3V
130
130
82
82
Z0 = 50
PECL
INPUTS
Z0 = 50
Figure 4. Alternative PECL-Output Termination
Applications Information
Alternative PECL-Output Termination
Figure 4 shows alternative PECL-output termination
methods. Use Thevenin-equivalent termination when a
(VCC - 2V) termination voltage is not available. If AC-
coupling is necessary, be sure that the coupling capac-
itor is placed following the 50
or Thevenin-equivalent
DC termination.
Layout Techniques
For best performance, use good high-frequency layout
techniques. Filter voltage supplies and keep ground
connections short. Use multiple vias where possible.
Also, use controlled-impedance transmission lines to
interface with the MAX3890 clock and data inputs and
outputs.
Exposed Pad (EP) Package
The EP 64-pin TQFP incorporates features that provide
a very low thermal resistance path for heat removal
from the IC to a PC board. The MAX3890’s exposed
pad must be soldered directly to a ground plane with
good thermal conductance.
Figure 3. Current-Mode Logic
50
50
VCC
SLBI+
SLBI-
VCC
50
50
SLBO+
SLBO-
GND
ESD
STRUCTURE
INPUT CIRCUIT
OUTPUT CIRCUIT
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