參數(shù)資料
型號(hào): MAX3880ECB+TD
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 8/12頁(yè)
文件大?。?/td> 0K
描述: IC 1:16 DESERIALIZER 64-TQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 750
功能: 解串器
數(shù)據(jù)速率: 2.5Gbps
輸入類(lèi)型: 串行
輸出類(lèi)型: LVDS
輸入數(shù): 1
輸出數(shù): 16
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 64-TQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 64-TQFP-EP(10x10)
包裝: 帶卷 (TR)
MAX3880
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
_______________________________________________________________________________________
5
NAME
FUNCTION
1, 17, 25, 33,
41, 49, 56,
62, 64
GND
Ground
PIN
Pin Description
2
FIL+
Positive Filter Input. PLL loop filter connection. Connect a 1.0F capacitor between FIL+ and FIL-.
3
FIL-
Negative Filter Input. PLL loop filter connection. Connect a 1.0F capacitor between FIL+ and FIL-.
4, 7, 10, 13,
24, 32, 40,
48, 57
VCC
+3.3V Supply Voltage
5
PHADJ+
Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCC if not
used.
6
PHADJ-
Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCC if not
used.
8
SDI+
Positive Serial Data Input. 2.488Gbps data stream.
9
SDI-
Negative Serial Data Input. 2.488Gbps data stream.
11
SLBI+
Positive System Loopback Input. 2.488Gbps data stream.
12
SLBI-
Negative System Loopback Input. 2.488Gbps data stream.
14
SIS
Signal Input Selection. TTL low for normal data input (SDI). TTL high for system loopback input
(SLBI).
15
SYNC-
Negative Synchronizing Pulse LVDS Input. Pulse the SYNC signal high for at least four serial-data
bit periods (1.6ns) to shift the data alignment by dropping 1 bit.
16
SYNC+
Positive Synchronizing Pulse LVDS Input. Pulse the SYNC signal high for at least four serial-data
bit periods (1.6ns) to shift the data alignment by dropping 1 bit.
18
PCLK-
Negative Parallel Clock LVDS Output
19
PCLK+
Positive Parallel Clock LVDS Output
20, 22, 26,
28, 30, 34,
36, 38, 42,
44, 46, 50,
52, 54, 58, 60
PD0- to
PD15-
Negative Parallel Data LVDS Outputs. Data is updated on the negative transition of the PCLK
signal (Figure 5).
21, 23, 27,
29, 31, 35,
37, 39, 43,
45, 47, 51,
53, 55, 59, 61
PD0+ to
PD15+
Positive Parallel Data LVDS Outputs. Data is updated on the negative transition of the PCLK
signal (Figure 5).
63
LOL
Loss-of-Lock Output. PLL loss-of-lock monitor, TTL active low (internal 10k
pull-up resistor). The
LOL monitor is valid only when a data stream is present on the inputs to the MAX3880.
EP
Exposed Pad
Ground. This must be soldered to a circuit board for proper thermal performance (see Package
Information).
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