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| 型號： | MAX3880ECB+TD |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 11/12頁 |
| 文件大小： | 0K |
| 描述： | IC 1:16 DESERIALIZER 64-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 750 |
| 功能： | 解串器 |
| 數(shù)據(jù)速率： | 2.5Gbps |
| 輸入類型： | 串行 |
| 輸出類型： | LVDS |
| 輸入數(shù)： | 1 |
| 輸出數(shù)： | 16 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-TQFP-EP（10x10） |
| 包裝： | 帶卷 (TR) |
MAX3880
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
8
_______________________________________________________________________________________
Low-Voltage Differential-Signal (LVDS)
Inputs and Outputs
The MAX3880 features LVDS inputs and outputs for
interfacing with high-speed digital circuitry. The LVDS
standard is based on the IEEE 1596.3 LVDS specifica-
tion. This technology uses 500mVp-p to 800mVp-p dif-
ferential low-voltage swings to achieve fast transition
times, minimize power dissipation, and improve noise
immunity. For proper operation, the parallel clock and
data LVDS outputs (PCLK+, PCLK-, PD_+, PD_-)
require 100
differential DC termination between the
positive and negative outputs. Do not terminate these
outputs to ground. The synchronization LVDS inputs
(SYNC+, SYNC-) are internally terminated with 100
differential input resistance and therefore do not require
external termination.
Design Procedure
Jitter Tolerance and Input
Sensitivity Trade-Offs
When the received data amplitude is higher than
50mVp-p, the MAX3880 provides a typical jitter toler-
ance of 0.46 UI at jitter frequencies greater than
10MHz. The SDH/SONET jitter tolerance specification is
0.15UI, leaving a jitter allowance of 0.31UI for receiver
preamplifier and postamplifier design.
The BER is better than 1 x 10-10 for input signals
greater than 9.5mVp-p. At 25mVp-p, jitter tolerance will
be degraded, but will still be above the SDH/SONET
requirement. Trade-offs can be made between jitter tol-
erance and input sensitivity according to the specific
application. See the Typical Operating Characteristics
for Jitter Tolerance and BER vs. Input Voltage graphs.
Applications Information
Consecutive Identical Digits (CIDs)
The MAX3880 has a low phase and frequency drift in
the absence of data transitions. As a result, long runs of
consecutive zeros and ones can be tolerated while
maintaining a BER of 1 x 10-10. The CID tolerance is
tested using a 213 - 1 pseudorandom bit stream
(PRBS), substituting a long run of zeros to simulate the
worst case. A CID tolerance of greater than 2,000 bits
is typical.
Phase Adjust
The internal clock is aligned to the center of the data
eye. For specific applications, this sampling position
can be shifted using the PHADJ inputs to optimize BER
performance. The PHADJ inputs operate with differen-
tial input voltages up to ±1.5V. A simple resistor-divider
with a bypass capacitor is sufficient to set these levels
(Figure 6). When the PHADJ inputs are not used, they
should be tied directly to VCC.
System Loopback
The MAX3880 is designed to allow system loopback
testing. The user can connect a serializer output
(MAX3890) in a transceiver directly to the SLBI+ and
SLBI- inputs of the MAX3880 for system diagnostics. To
select the SLBI± inputs, apply a TTL logic high to the
SIS pin.
PCLK
PD0–PD15
NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, PCLK = (PCLK+) - (PCLK-).
tCLK-Q
Figure 5. Timing Parameters
MAX3880
PHADJ+ (PIN 5)
PHADJ- (PIN 6)
3.3V
Figure 6. Phase-Adjust Resistor-Divider
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX3881ECB | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| MAX3881ECB+D | 功能描述:串行器/解串器 - Serdes Integrated Circuits (ICs) RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX3881ECB+TD | 功能描述:串行器/解串器 - Serdes Integrated Circuits (ICs) RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX3881ECB-D | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX3881ECB-TD | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
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