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參數(shù)資料
| 型號(hào)： | MAX3880ECB+TD |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 1:16 DESERIALIZER 64-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 功能： | 解串器 |
| 數(shù)據(jù)速率： | 2.5Gbps |
| 輸入類型： | 串行 |
| 輸出類型： | LVDS |
| 輸入數(shù)： | 1 |
| 輸出數(shù)： | 16 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-TQFP-EP（10x10） |
| 包裝： | 帶卷 (TR) |
MAX3880
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
_______________________________________________________________________________________
7
dropped, shifting the alignment between PCLK and
data by 1 bit. The SYNC signal must be at least four
serial bit periods wide (4 x 402ps). See Figure 4 for the
timing diagram and Figure 5 for the timing parameters
diagram.
Input Amplifier
The input amplifiers on both the main data and system
loopback accept a differential input amplitude from
50mVp-p to 800mVp-p. The bit error rate (BER) is bet-
ter than 1 x 10-10 for input signals as small as 9.5mVp-
p, although the jitter tolerance performance will be
degraded. For interfacing with PECL signal levels, see
Applications Information.
Phase Detector
The phase detector in the MAX3880 produces a volt-
age proportional to the phase difference between the
incoming data and the internal clock. Because of its
feedback nature, the PLL drives the error voltage to
zero, aligning the recovered clock to the center of the
incoming data eye for retiming. The external phase
adjust pins (PHADJ+, PHADJ-) allow the user to vary
the internal phase alignment.
Frequency Detector
The digital frequency detector (FD) aids frequency
acquisition during start-up conditions. The frequency
difference between the received data and the VCO
clock is derived by sampling the in-phase and quadra-
ture VCO outputs on both edges of the data input sig-
nal. Depending on the polarity of the frequency
difference, the FD drives the VCO until the frequency
difference is reduced to zero. Once frequency acquisi-
tion is complete, the FD returns to a neutral state. False
locking is completely eliminated by this digital frequen-
cy detector.
Loop Filter and VCO
The phase detector and frequency detector outputs are
summed into the loop filter. A 1.0F capacitor, CF, is
required to set the PLL damping ratio.
The loop filter output controls the on-chip LC VCO run-
ning at 2.488GHz. The VCO provides low phase noise
and is trimmed to the correct frequency.
Loss-of-Lock Monitor
A loss-of-lock (LOL) monitor is included in the
MAX3880 frequency detector. A loss-of-lock condition
is signaled immediately with a TTL low. When the PLL is
frequency-locked, LOL switches to TTL high in approxi-
mately 800ns.
Note that the LOL monitor is only valid when a data
stream is present on the inputs to the MAX3880. As a
result, LOL does not detect a loss-of-power condition
resulting from a loss of the incoming signal.
SDI
SYNC
PCLK
D0
D15
D14
D13
D16
D32
D48
1 BIT HAS SLIPPED
IN THIS TIME SLICE
D65
(LSB) PD0
D1
D17
D33
D49
D66
PD1
D15
(MSB)
TRANSMITTED FIRST
D31
D47
D64
D80
PD15
Figure 4. Timing Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX3881ECB | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| MAX3881ECB+D | 功能描述:串行器/解串器 - Serdes Integrated Circuits (ICs) RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX3881ECB+TD | 功能描述:串行器/解串器 - Serdes Integrated Circuits (ICs) RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX3881ECB-D | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX3881ECB-TD | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
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