參數(shù)資料
型號: MAX3770CEE
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 通信及網(wǎng)絡
英文描述: 2.125Gbps/1.063Gbps, 3.3V Fibre Channel Repeaters
中文描述: SPECIALTY TELECOM CIRCUIT, PDSO16
封裝: 0.150 INCH, 0.025 INCH PITCH, QSOP-16
文件頁數(shù): 6/8頁
文件大?。?/td> 564K
代理商: MAX3770CEE
M
2.125Gbps/1.063Gbps, 3.3V
Fibre Channel Repeaters
6
_______________________________________________________________________________________
Detailed Description
Figure 2 shows the functional diagram of the MAX3770
Fibre Channel repeater IC. The MAX3770 consists of a
fully integrated phased-lock loop (PLL), CML input and
output buffers, and a data latch. The PLL consists of a
phase/frequency detector (PFD), a loop filter, and a
voltage-controlled oscillator (VCO). The input and out-
put signal buffers employ low-noise CML architecture
and are terminated on-chip.
Phase and Frequency Detector
The phase/frequency detector generates an output signal
that reflects the phase relationship between the incoming
data and the internal clock generated by the VCO. Data
recovery is accomplished by feedback in the PLL, which
drives the error voltage to zero, aligning the falling edge
of the recovered clock to the center of the data eye.
The phase frequency detector generates a frequency
lock indication that can be monitored at the LOCK pin
(Table 1). When the PLL is frequency-locked onto the
incoming data, lock transitions high.
VCO and Latch
The fully integrated VCO contains an internal current ref-
erence and filter circuitry to minimize the influence
of V
CC
noise. The VCO is trimmed to 2.125GHz
(MAX3770) and creates a clock output with frequency
proportional to the control voltage applied by the loop
filter. Data recovery is accomplished by using the recov-
ered clock signal to latch the incoming data to the CML
output buffers, significantly reducing the output jitter.
Applications Information
Figures 3 and 4 show models for the MAX3770/MAX3771
inputs and outputs, including package parasitics. Figure
5 shows typical 50
termination applications.
Design Procedure
The MAX3770
s performance can be greatly affected
by circuit board layout and design. Use good high-fre-
quency design techniques, including minimizing
ground inductance and using fixed-impedance trans-
mission lines on the data and clock signals. All IN,
OUT, and CLK pins can be connected with 0.1μF or
0.01μF coupling capacitors. If DC coupling is desired,
pay particular attention to the DC voltage and current
requirements at the pins of interest (see
DC Electrical
Characteristics
). The MAX3750/MAX3751 port bypass
circuit can be DC-coupled to the MAX3770/MAX3771
repeater. A 0.22μF capacitor should be used for the
loop filter.
Control Functions
The lock enable (LOCKEN) and clock enable (CLKEN)
pins can be configured to control the PLL
s clock.
Table 1 shows the operational modes available.
Figure 3. Input Structure
Figure 4. Output Structure
ESD
STRUCTURES
IN+
0.2pF
PACKAGE
1.5nH
1.5nH
0.4pF
0.4pF
V
CC
- 0.450V
0.2pF
75
75
1k
V
CC
ESD
STRUCTURES
10.5mA
OUT-
OUT+
0.2pF
V
CC
PACKAGE
1.5nH
1.5nH
0.4pF
0.4pF
0.2pF
75
75
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