參數資料
型號: MAX3770CEE
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 通信及網絡
英文描述: 2.125Gbps/1.063Gbps, 3.3V Fibre Channel Repeaters
中文描述: SPECIALTY TELECOM CIRCUIT, PDSO16
封裝: 0.150 INCH, 0.025 INCH PITCH, QSOP-16
文件頁數: 4/8頁
文件大?。?/td> 564K
代理商: MAX3770CEE
M
2.125Gbps/1.063Gbps, 3.3V
Fibre Channel Repeaters
4
_______________________________________________________________________________________
MAX3770
JITTER TRANSFER
M
JITTER FREQUENCY (Hz)
J
5
-20
-25
-15
-10
-5
0
1k
1M
10M
100M
10k
100k
1G
CJTPAT
V
CC
= 3.3V
C
F
= 0.1
μ
F
MAX3770
JITTER TOLERANCE
M
JITTER FREQUENCY (Hz)
S
0.01
0.1
1
10
1M
10M
100M
10k
100k
CJTPAT
V
CC
= 3.3V
C
F
= 0.1
μ
F
ADDITIONAL 0.6UI DJ AND RJ
APPLIED ABOVE 10MHz
FIBRE CHANNEL
SINUSOIDAL
JITTER MASK
DATA
V
CC
= 3.3V
CJTPAT
VCLK-
CLOCK
MAX3770
RECOVERED DATA AND CLOCK SIGNALS
M
100ps/div
Typical Operating Characteristics
(V
CC
= +3.3V, T
A
= +25
°
C, unless otherwise noted.)
Pin Description
NAME
PIN
FUNCTION
1
FILT+
PLL Loop Filter Connection. Connect a 0.22μF capacitor between FILT+ and FILT-.
2
FILT-
PLL Loop Filter Connection. Connect a 0.22μF capacitor between FILT+ and FILT-.
3, 6, 12
GND
Ground
4
IN+
Positive CML Data Input (Figure 3)
5
IN-
Negative CML Data Input (Figure 3)
7, 8
V
CC
Supply Voltage
9
LOCKEN
When this input is forced high, the lock indicator is enabled. Ground for normal operation.
10
OUT-
Negative 75
CML Data Output (Figure 4)
11
OUT+
Positive 75
CML Data Output (Figure 4)
13
CLKEN
When this input is forced high, the clock output is enabled. Ground for normal operation.
14
CLK-
Negative 75
CML Clock Output (Figure 4). Enabled when CLKEN is forced high; disabled when CLKEN
is forced low.
15
CLK+
Positive 75
CML Clock Output (Figure 4). Enabled when CLKEN is forced high; disabled when CLKEN is
forced low.
16
LOCK
Frequency Lock Indicator. High level indicates the PLL is frequency-locked. Disabled when LOCKEN is
forced low. The output of the LOCK pin may chatter when large jitter is applied to the input.
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