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參數(shù)資料
| 型號： | MAX3676 |
| 廠商： | Maxim Integrated Products, Inc. |
| 元件分類： | 運動控制電子 |
| 英文描述： | 622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier |
| 中文描述： | 622Mbps、3.3V時鐘恢復與數(shù)據(jù)再定時IC，帶有限幅放大器 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大小： | 181K |
| 代理商： | MAX3676 |
M
622Mbps, 3.3V Clock-Recovery and
Data-Retiming IC with Limiting Amplifier
8
_______________________________________________________________________________________
Phase Detector
The phase detector produces a voltage proportional to
the phase difference between the incoming data and
the internal clock. Because of its feedback nature, the
PLL drives the error voltage to zero, aligning the recov-
ered clock to the incoming data. The external phase
adjustment pins (PHADJ+, PHADJ-) allow the user to
vary the internal phase alignment.
Frequency Detector
The frequency detector incorporated into the PLL uses
the input data stream edges to sample the quadrature
components of the VCO clock. This generates a differ-
ence frequency that aids acquisition during start-up.
Depending on the polarity of the difference frequency,
the PFD drives the VCO so that the difference frequen-
cy is reduced to zero. Once frequency acquisition is
obtained, the frequency detector returns to a neutral
state.
Loop Filter and VCO
The VCO is fully integrated, while the loop filter requires
an external R-C network. This filter network determines
the bandwidth and peaking of the second-order PLL.
__________________Design Procedure
Received-Signal-Strength Indicator
The RSSI output voltage is insensitive to temperature
and supply fluctuations. The power detector functions
as a broadband power meter that detects the total RMS
power of all signals within the detector bandwidth
(including input signal noise). The RSSI voltage varies
linearly (in decibels) for inputs of 2mVp-p to 50mVp-p.
The slope over this input range is approximately
26mV/dB.
The high-speed RSSI signal is filtered to an RMS level
with one external capacitor tied from CFILT to V
CC
. The
impedance looking into CFILT is about 500
to V
CC
. As
a result, the lower -3dB cutoff frequency is set by the
following simple relationship:
[
For 622Mbps applications, Maxim recommends a cut-
off frequency of 6.8kHz, which requires C
F
= 47nF. The
RSSI output is designed to drive a minimum load resis-
tance of 100k
to ground and a maximum of 20pF.
Loads greater than 20pF must be buffered by a series
resistance of 100k
(i.e., voltmeter).
Input Offset Correction
The on-chip limiting amplifier provides more than 42dB
of gain. A low-frequency feedback loop is integrated
into the MAX3676 to remove the input offset. DC-cou-
pling to the ADI+ and ADI- inputs is not allowed, as this
would prevent the proper functioning of the DC offset-
correction circuitry.
The differential input impedance (Z
IN
) is approximately
2.5k
. The impedance between OLC+ and OLC- (Z
OLC
)
is approximately 120k
. Take care when setting the
combined low-frequency cutoff (f
CUTOFF
), due to the
input DC-blocking capacitor (C
IN
) and the offset correc-
tion loop capacitor (C
OLC
). See Table 1 for selecting the
values of C
IN
and C
OLC
.
These values ensure that the poles associated with C
IN
and C
OLC
work together to provide a flat response at the
lower -3dB corner frequency (no gain peaking).
C
IN
must be a low-TC, high-quality capacitor of type X7R
or better in order to minimize f
CUTOFF
deviations. C
OLC
must be a capacitor of type Z5U or better.
Loss-of-Power Monitor
An LOP monitor with a user-programmable threshold
and a hysteresis comparator is also included with the
limiting amplifier circuitry. Internally, one comparator
input is tied to the RSSI output signal, and the other is
tied to the threshold voltage (V
TH
), which is set exter-
nally and provides a trip point for the LOP indication. A
low-voltage, low-drift op amp, referenced to an internal
bandgap voltage (1.23V), is supplied for programming
a supply independent threshold voltage. This op amp
requires two external resistors to program the LOP trip
point. V
TH
is programmable from 1.23V to 2.6V using
the equation:
V
= 1.23 1 + R2 / R1
TH
The op amp can source only 100μA of current.
Therefore, an R1 value of 20k
is recommended for
proper operation. The input bias current of the op amp
at the INV pin is less than ±100nA.
)
f
= 1 / 2 500
FILT
π
(
)
]
C
F
C
OLC
COMBINED LOW
f
CUTOFF
(kHz)
3.0
2200pF
1000pF
470pF
330pF
220pF
0.015μF
0.01μF
3300pF
2200pF
1500pF
29
68
135
190
290
C
IN
Table 1. Setting the Low-Frequency Cutoff
4700pF
0.033μF
13.5
6800pF
0.082μF
10
0.010μF
0.1μF
6.8
0.022μF
0.15μF
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX3676E/D | 功能描述:計時器和支持產(chǎn)品 RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內部定時器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| MAX3676E/D DIE | 制造商:Maxim Integrated Products 功能描述: |
| MAX3676E/D+ | 功能描述:計時器和支持產(chǎn)品 RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內部定時器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| MAX3676EHJ | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 622Mbps 3.3V Clock Recovery RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX3676EHJ+ | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 622Mbps 3.3V Clock Recovery RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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