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參數(shù)資料
| 型號(hào)： | MAX3675EHJ |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 622Mbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier |
| 中文描述： | CLOCK RECOVERY CIRCUIT, PQFP32 |
| 封裝： | 5 X 5 MM, 1 MM HEIGHT, MS-026AAA, TQFP-32 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 190K |
| 代理商： | MAX3675EHJ |
M
622Mbps, Low-Power, 3.3V Cloc k-Rec overy
and Data-Retiming IC with Limiting Amplifier
_______________________________________________________________________________________
7
_______________Detailed Desc ription
The block diagram in Figure 1 shows the MAX3675’s
architecture. It consists of a limiting amplifier input
stage followed by a fully integrated clock/data-recovery
(CDR) block implemented with a phase-locked loop
(PLL). The input stage is selectable between a limiting
amplifier or a simple PECL input buffer. The limiting
amplifier provides a loss-of-power (LOP) monitor and a
received-signal-strength indicator (RSSI). The PLL con-
sists of a phase/frequency detector (PFD), a loop filter
amplifier, and a voltage-controlled oscillator (VCO).
Limiting Amplifier
The MAX3675’s on-chip limiting amplifier accepts an
input signal level from 3.0mVp-p to 1.2Vp-p. The ampli-
fier consists of a cascade of gain stages that include
full-wave logarithmic detectors. The combined small-
signal gain is approximately 42dB, and the -3dB band-
width is 800MHz. Input-referred noise is less than
100μV
RMS
, providing excellent sensitivity for small-
amplitude data streams.
In addition to driving the CDR, the limiting amplifier pro-
vides both an RSSI output and an LOP monitor that
allow the user to program the threshold voltage. The
RSSI circuitry provides an output voltage that is linearly
proportional to the input power (in decibels) detected
between the ADI+ and ADI- input pins and is sensitive
enough to reliably detect signals as small as 2mVp-p.
Input DC offset reduces the accuracy of the power
detector; therefore, an integrated feedback loop is
included that automatically nulls the input offset of the
gain stage. The addition of this offset-correction loop
requires that the input signal be AC coupled when
using the ADI+ and ADI- inputs.
Finally, for applications that do not require the limiting
amplifier, selecting the digital inputs conserves power
by turning off the post-amplifier block.
MAX3675
LOL
PHASE/FREQ
DETECTOR
POWER
DETECT
OFFSET
CORRECTION
FILTER
622.08MHz
LIMITER
42dB
BIAS
VCO
Σ
D
Q
Q
I
CFILT
RSSI
INV
VTH
LOP
FIL+ FIL-
PHADJ+
DDI+
DDI-
INSEL
ADI-
ADI+
PHADJ-
1.18V
SDO+
SDO-
PECL
V
CC
V
CC
6k
6k
PECL
PECL
SCLKO+
SCLKO-
OLC+
OLC-
Figure 1. Functional Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX3675EHJEVKIT | 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| MAX3675EHJ-T | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX3676E/D | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| MAX3676E/D DIE | 制造商:Maxim Integrated Products 功能描述: |
| MAX3676E/D+ | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
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