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參數(shù)資料
| 型號(hào)： | MAX3675 |
| 廠商： | Maxim Integrated Products, Inc. |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | 622Mbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier |
| 中文描述： | 622Mbps、低功耗、3.3V時(shí)鐘恢復(fù)與數(shù)據(jù)再定時(shí)IC，帶有限幅放大器 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大小： | 190K |
| 代理商： | MAX3675 |
M
622Mbps, Low-Power, 3.3V Cloc k-Rec overy
and Data-Retiming IC with Limiting Amplifier
_______________________________________________________________________________________
9
current of the op amp at the INV pin is guaranteed to
be less than ±100nA. To set the threshold voltage
externally (i.e., via a DAC control), completely disable
the op amp by grounding the inverting terminal (INV).
V
TH
then becomes high impedance and must be driven
externally.
The comparator is configured with an active-high LOP
output. An on-chip, 6k
pull-up resistor is provided to
reduce external part count.
S etting the Loop Filter
The loop filter within the PLL consists of a transconduc-
tance amplifier and external filter elements R
F
and C
F
(Figure 2). The closed-loop bandwidth of a PLL is
approximated by:
K K Gm R
where K
D
is the gain of the phase detector, K
O
is the
gain of the VCO, and Gm is the transconductance of
the filter amplifier. For the MAX3675, an estimated value
of K
D
K
O
Gm is 7k.
Because the PLL is a second-order system, a zero in
the open-loop gain is required for stability. This zero is
set by the following equation:
ω
z
= 1 / R C
where the recommended external value of C
F
is 2.2μF.
Increasing the value of R
F
increases the PLL bandwidth
(f
LOOP
). Increasing this bandwidth improves jitter toler-
ance and jitter-generation performance, but also
reduces jitter-transfer performance. (Decreasing the
bandwidth has the opposite effect.)
This type of PLL is a classical second-order system.
Therefore, as f
z
(the frequency of the zero) approaches
f
LOOP
, the jitter-transfer peaking increases. For an over-
damped system (f
z
/f
LOOP
) < 0.25, the jitter peaking of a
second-order system can be approximated by:
Mp = 1 - (f
z
/ f
LOOP
)
where Mp is the magnitude of the peaking. For
(f
z
/f
LOOP
) < 0.1, this equation holds to within 10%.
C
F
can be made smaller if meeting the jitter-transfer
specifications is not a requirement. For example, setting
R
F
to 300
and C
F
to 3.3nF increases the loop band-
width to approximately 2.2MHz (Figure 3). Loop stability
is ensured by maintaining a separation of 10x between
f
LOOP
and f
z
. Be careful when changing the value of R
F
.
Lower values of R
F
are limited by the internal resistance
of the IC, and upper values are limited by the internal
high-frequency pole.
F
)
F
MAX3675
F(S)
C
F
R
F
GM
FIL+
FIL-
Figure 2. Loop Filter
F(s) =
Gm
s
s C s/
1
R C
52 3
R
C
ω
P
2.2 F
internal higher-order pole
z
ω
P
F
ω
ω
+
)
+
[
]
=
=
=
=
1
1
z
.
100
1k
10k
100k
1M
10M
100M
1G
M
FREQUENCY (Hz)
G
f
Z
= 1.38kHz
C
F
= 2.2
μ
F
HIGHER-
ORDER
POLE
>10x
f
LOOP
= 375kHz
R
F
f
LOOP
= K
S
K
O
G
m
R
F
f
Z
= 161kHz
C
F
= 3.3nF
f
LOOP
= 2.2MHz
R
Figure 3. Loop-Filter Response
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX3675E/D | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX3675E/D DIE | 制造商:Maxim Integrated Products 功能描述: |
| MAX3675ECJ | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX3675ECJ.B50011 | 制造商:Maxim Integrated Products 功能描述: |
| MAX3675ECJ.G044 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
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