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參數(shù)資料
| 型號： | MAX194 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 14-Bit, 85ksps ADC with 10礎 Shutdown(85ksps,單通道,14位串行A/D轉換器) |
| 中文描述： | 14位、85ksps ADC，帶有10µ關斷 |
| 文件頁數(shù)： | 17/24頁 |
| 文件大小： | 267K |
| 代理商： | MAX194 |
Data is clocked out of the MAX194 on CLK’s falling
edge and can be clocked into the μP on the rising
edge or the following falling edge. If you clock data in
on the rising edge (SPI/QSPI with CPOL = 0 and CPHA
= 0; standard Microwire: Hitachi H8), the maximum
CLK rate is given by:
1
f
CLK
(max) =
1
2
x —————
t
CD
+ t
SD
where t
CD
is the MAX194’s CLK-to-DOUT valid delay
and t
SD
is the data setup time for your μP.
If clocking data in on the falling edge (CPOL = 0, CPHA
= 1), the maximum CLK rate is given by:
1
f
CLK
(max) = —————
t
CD
+ t
SD
Do not exceed the maximum CLK frequency given in
the Electrical Characteristics table. To clock data in on
the falling edge, your processor hold time must not
exceed t
CD
minimum (100ns).
While QSPI can provide the required 20 CLK cycles as
two continuous 10-bit transfers, SPI is limited to 8-bit
transfers. This means that with SPI, a conversion must
consist of three 8-bit transfers. Ensure that the pauses
between 8-bit operations at your selected clock rate
are short enough to maintain a 20ms or shorter conver-
sion time, or the leakage of the capacitive DAC may
cause errors.
M
14-Bit, 85ksps ADC with 10μA S hutdown
______________________________________________________________________________________
17
EOC
CLK
t
CD
t
DV
DATA LATCHED:
t
DH
CS, CONV
DOUT
B13 FROM PREVIOUS
CONVERSION
B13
B13
B0
B12
S1
S0
MAX194
QSPI
GPT
BP/UP/SHDN
SCLK
EOC
DOUT
RESET
CONV
1.7MHz
CLK
IC3
CS
OC3
SCK
IC1
MISO
OC2
START
PCS0
1.3
μ
s
74HC32
Figure 19. MAX194 Connection to QSPI Processor Clocking
Data Out with SCLK Between Conversions
Figure 18. Timing Diagram for Circuit of Figure 17
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