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參數(shù)資料
| 型號： | MAX1712 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs |
| 中文描述： | 高速、數(shù)字可調(diào)、降壓型控制器，用于筆記本電腦 |
| 文件頁數(shù)： | 20/28頁 |
| 文件大?。?/td> | 437K |
| 代理商： | MAX1712 |
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input voltage don’t exceed the package ratings or violate
the overall thermal budget.
Choose a low-side MOSFET (Q2) that has the lowest
possible R
DS(ON)
, comes in a moderate to small pack-
age (i.e., SO-8), and is reasonably priced. Ensure that
the MAX1710/MAX1711/MAX1712 DL gate driver can
drive Q2; in other words, check that the gate isn’t pulled
up by the high-side switch turning on due to parasitic
drain-to-gate capacitance, causing cross-conduction
problems. Switching losses aren’t an issue for the low-
side MOSFET since it’s a zero-voltage switched device
when used in the buck topology.
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET, the worst-case
power dissipation due to resistance occurs at minimum
battery voltage:
PD(Q1) = (V
OUT
/ V
BATT(MIN)
)
I
LOAD
2
R
DS(ON)
Generally, a small high-side MOSFET is desired in order
to reduce switching losses at high input voltages.
However, the R
DS(ON)
required to stay within package
power-dissipation limits often limits how small the MOS-
FET can be. Again, the optimum occurs when the switch-
ing (AC) losses equal the conduction (R
DS(ON)
) losses.
High-side switching losses don’t usually become an
issue until the input is greater than approximately 15V.
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied, due to the squared term in the
CV
2
F switching loss equation. If the high-side MOSFET
you’ve chosen for adequate R
DS(ON)
at low battery volt-
ages becomes extraordinarily hot when subjected to
V
BATT(MAX)
, you must reconsider your choice of MOS-
FET.
Calculating the power dissipation in Q1 due to switching
losses is difficult, since it must allow for difficult-to-quanti-
M
High-Speed, Digitally Adjusted
Step-Down Controllers for Notebook CPUs
20
______________________________________________________________________________________
V+
SHDN
SKIP
V
CC
V
IN
= 7V TO 24V*
REF
DAC
INPUTS
ON/OFF
CC
0.22
μ
F
470pF
DL
D0
D1
D2
D3
D4
LX
BST
5
DH
PGND
GND
FB
Q1
+5V
20
0.1
μ
F
1
μ
F
Q2
0.5
μ
H
0.1
μ
F
1nF
C1
1k
R1
C2
CPU
1.6V AT 7A
1k
1k
V
DD
FBS
GNDS
MAX1711
MAX1712
R2
C1 = 4 x 4.7
μ
F/25V TAIYO YUDEN (TMK325BJ475K)
C2 = 6 x 47
μ
F/10V TAIYO YUDEN (LMK550BJ476KM)
R1 + R2 = 5m
MINIMUM OF PC BOARD TRACE RESISTANCE (TOTAL)
TON
*FOR HIGHER MINIMUM INPUT VOLTAGE,
*
LESS OUTPUT CAPACITANCE IS REQUIRED.
Figure 7. All-Ceramic-Capacitor Application
TON
SETTING
(kHz)
APPROXIMATE
K-FACTOR
ERROR (%)
MIN V
BATT
AT V
OUT
= 2V
(V)
200
±10
2.6
300
±10
2.9
400
±12.5
3.2
550
±12.5
3.6
K
FACTOR
(μs-V)
5
3.3
2.5
1.8
Table 6. Approximate K-Factors Errors
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