參數(shù)資料
型號(hào)： MAX1434ECQ+TD
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 3/22頁(yè)
文件大?。?/td> 0K
描述： IC ADC 10BIT 50MSPS 100-TQFP
標(biāo)準(zhǔn)包裝： 500
位數(shù)： 10
采樣率（每秒）： 50M
數(shù)據(jù)接口： LVDS，串行
轉(zhuǎn)換器數(shù)目： 8
功率耗散（最大）： 882mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： *
封裝/外殼： 100-TQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 8 個(gè)差分
MAX1434
Octal, 10-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
______________________________________________________________________________________
11
PIN
NAME
FUNCTION
58
FRAMEN
Negative Frame-Alignment LVDS/SLVS Output. A rising edge on the differential FRAME
output aligns to a valid D0 in the output data stream.
59
FRAMEP
Positive Frame-Alignment LVDS/SLVS Output. A rising edge on the differential FRAME output
aligns to a valid D0 in the output data stream.
61
CLKOUTN
Negative LVDS/SLVS Serial Clock Output
62
CLKOUTP
Positive LVDS/SLVS Serial Clock Output
65
OUT3N
Channel 3 Negative LVDS/SLVS Output
66
OUT3P
Channel 3 Positive LVDS/SLVS Output
68
OUT2N
Channel 2 Negative LVDS/SLVS Output
69
OUT2P
Channel 2 Positive LVDS/SLVS Output
72
OUT1N
Channel 1 Negative LVDS/SLVS Output
73
OUT1P
Channel 1 Positive LVDS/SLVS Output
78
OUT0N
Channel 0 Negative LVDS/SLVS Output
79
OUT0P
Channel 0 Positive LVDS/SLVS Output
80
LVDSTEST
LVDS Test Pattern Enable. Drive LVDSTEST high to enable the output test pattern
(0001011101 MSB
→ LSB). As with the analog conversion results, the test pattern data is
output LSB first. Drive LVDSTEST low for normal operation.
81
PD
Power-Down Input. Drive PD high to power down all channels and reference. Drive PD low for
normal operation.
82
PLL3
PLL Control Input 3. See Table 1 for details.
83
PLL2
PLL Control Input 2. See Table 1 for details.
84
PLL1
PLL Control Input 1. See Table 1 for details.
85
T/B
Output Format-Select Input. Drive T/B high to select binary output format. Drive T/B low to
select two’s-complement output format.
90
REFN
Negative Reference Bypass Output. Connect a
≥ 1F (10F typ) capacitor between REFP and
REFN, and connect a
≥ 1F (10F typ) capacitor between REFN and GND. Place the
capacitors as close as possible to the device on the same side of the PCB.
91
REFP
Positive Reference Bypass Output. Connect a
≥ 1F (10F typ) capacitor between REFP and
REFN, and connect a
≥ 1F (10F typ) capacitor between REFP and GND. Place the
capacitors as close as possible to the device on the same side of the PCB.
93
REFIO
Reference Input/Output. For internal reference operation (REFADJ = GND), the reference
output voltage is 1.24V. For external reference operation (REFADJ = AVDD), apply a stable
reference voltage at REFIO. Bypass to GND with
≥ 0.1F.
94
REFADJ
Internal/External Reference-Mode-Select and Reference Adjust Input. For internal reference
mode, connect REFADJ directly to GND. For external reference mode, connect REFADJ
directly to AVDD. For reference-adjust mode, see the Full-Scale Range Adjustments Using the
Internal Reference section.
95
CMOUT
Common-Mode Reference Voltage Output. CMOUT outputs the input common-mode voltage
for DC-coupled applications. Bypass CMOUT to GND with
≥ 0.1F capacitor.
97
IN0P
Channel 0 Positive Analog Input
98
IN0N
Channel 0 Negative Analog Input
—
EP
Exposed Pad. EP is internally connected to GND. Connect EP to GND.
Pin Description (continued)
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